soc/amd/*/acpi: Add root complex ACPI device

The Root complex always resides at 0:0.0 and is always enabled.
Add a static device in DSDT that can be extended later on.

Change-Id: I1d45f7cd732c41343ac154c313a7ca368b0ea2b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91183
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2026-02-12 16:05:59 +01:00 committed by Matt DeVillier
commit e95ed7aecf
6 changed files with 50 additions and 1 deletions

View file

@ -7,6 +7,16 @@
* Currently the name is hex representation of dev->path.pci.devfn.
*/
/* Root complex */
Device (GNB)
{
Name (_ADR, 0)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
}
/* PCIe GPP */
ACPI_PCI_DEV(GP09, 1, 1)
ACPI_PCI_DEV(GP0A, 1, 2)

View file

@ -93,7 +93,6 @@ static void root_complex_fill_ssdt(const struct device *device)
* }
* }
*/
acpi_device_write_pci_dev(device);
acpigen_write_scope(acpi_device_path(device));
struct opregion opreg = OPREGION("SMN", SYSTEMMEMORY,
CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xb8, 0x8);

View file

@ -7,6 +7,16 @@
* Currently the name is hex representation of dev->path.pci.devfn.
*/
/* Root complex */
Device (GNB)
{
Name (_ADR, 0)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
}
/* USB4.0 bridge */
ACPI_PCI_DEV(GP09, 1, 1)
ACPI_PCI_DEV(GP0A, 1, 2)

View file

@ -7,6 +7,16 @@
* Currently the name is hex representation of dev->path.pci.devfn.
*/
/* Root complex */
Device (GNB)
{
Name (_ADR, 0)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
}
/* PCIe GPP */
ACPI_PCI_DEV(GP11, 2, 1)
ACPI_PCI_DEV(GP12, 2, 2)

View file

@ -7,6 +7,16 @@
* Currently the name is hex representation of dev->path.pci.devfn.
*/
/* Root complex */
Device (GNB)
{
Name (_ADR, 0)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
}
/* PCIe GPP */
ACPI_PCI_DEV(GP09, 1, 1)
ACPI_PCI_DEV(GP0A, 1, 2)

View file

@ -7,6 +7,16 @@
* Currently the name is hex representation of dev->path.pci.devfn.
*/
/* Root complex */
Device (GNB)
{
Name (_ADR, 0)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
}
/* PCIe GPP */
ACPI_PCI_DEV(GP09, 1, 1)
ACPI_PCI_DEV(GP0A, 1, 2)