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soc/intel/pantherlake: Enable all RootPorts on PTL-H484

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According to EDS #872188, PTL-H484 has 8 more PCIe
lanes than PTL-H404 and 12Xe SKUs.

I believe there's been a mixup during bringup, as PCIe ACPI tables are
"gated" for an SKU with more PCIe 5.0 lanes.

To be exact, in a file: "src/soc/intel/pantherlake/acpi/ptl_pcie.asl"
we can notice PCIe 5.0 RootPorts depending on SOC_INTEL_PANTHERLAKE_H.
Google/Fatcat boards seem to be using PANTHERLAKE_U_H instead.

TEST: Build/boot intel/pantherlake_crb. Make sure Linux doesn't report
PCIe routing errors.

Change-Id: I1d136cf1959a3851d0ac37b256fd4df28a8d30df
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Alicja Michalska 2026-01-22 02:03:56 +01:00 • committed by Matt DeVillier
commit 261274992d
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/pantherlake/Kconfig
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@ -253,8 +253,8 @@ config MAX_TBT_ROOT_PORTS
config MAX_ROOT_PORTS
int
default 6 if SOC_INTEL_WILDCATLAKE
default 10 if SOC_INTEL_PANTHERLAKE_H
default 12
default 12 if SOC_INTEL_PANTHERLAKE_H
default 10
config MAX_PCIE_CLOCK_SRC
int