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soc/intel/pantherlake: Consolidate WCL SKUs and update GT VR settings

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Simplify Wildcat Lake SKU configuration by consolidating multiple
SKU variants into a single WCL_SKU_1 configuration. All WCL device
IDs (WCL_ID_2 through WCL_ID_5) now map to WCL_SKU_1 instead of
having separate SKU definitions.

Additionally, update GT domain VR controller settings for WCL_SKU_1:
 - Set IccMax to 36A (144 in register units) for GT domain

BUG=b:467349691
TEST=Build ocelot and verify system boots with consolidated WCL SKU
configuration. Confirm GT VR IccMax is set to 36A in coreboot logs.

Change-Id: I6466c150bcd712430cf2595db5be13039688fecb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Appukuttan V K 2026-01-19 23:31:54 +05:30 • committed by Nick Vaccaro
commit 051516af1a
2 changed files with 8 additions and 8 deletions
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12
src/soc/intel/pantherlake/chip.h
View file

@ -78,10 +78,6 @@ enum soc_intel_pantherlake_sku {
PTL_SKU_6,
PTL_SKU_7,
WCL_SKU_1,
WCL_SKU_2,
WCL_SKU_3,
WCL_SKU_4,
WCL_SKU_5,
MAX_PTL_SKUS,
};
@ -119,10 +115,10 @@ static const struct soc_intel_pantherlake_power_map {
{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_7, PTL_TDC_4 },
{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 },
{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2, WCL_TDC_1 },
{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3, WCL_TDC_1 },
{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4, WCL_TDC_1 },
{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5, WCL_TDC_1 },
{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 },
};
/* Types of display ports */

4
src/soc/intel/pantherlake/chipset_wcl.cb
View file

@ -8,6 +8,10 @@ chip soc/intel/pantherlake
.tdp_pl4 = 93,
}"
register "icc_max[WCL_SKU_1]" = "{
[VR_DOMAIN_GT] = 36 * 4,
}"
# Reduce the size of BasicMemoryTests to speed up the boot time.
register "lower_basic_mem_test_size" = "true"