Patrick Rudolph 4e61dd36e4 soc/amd/cezanne: Move SSDT code into DSDT ... Now that the ACP device is always present in DSDT move the MSG0 method and helper functions into DSDT. This allows to clean the common ACP code and reduces differences in the runtime code pathes. The newly introduced DSDT is also verified at compile time. Change-Id: Ifc55278aa66abcb54691017738cc843e3088d8e8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91159 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2026-02-17 14:22:52 +00:00
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amd	soc/amd/cezanne: Move SSDT code into DSDT	2026-02-17 14:22:52 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/pantherlake: Fill in SPD data on both channels of DDR5 memory	2026-02-15 13:57:52 +00:00
mediatek	soc/mediatek/common: Combine dsi_cmdq_size register writes	2026-01-25 19:06:22 +00:00
nvidia	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
qualcomm	soc/qualcomm/x1p42100: Add support to invoke LPASS Init	2026-02-12 17:23:48 +00:00
rockchip	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00