Introduces logo_bottom_margin to soc_intel_common_config to allow
adjusting the vertical (or horizontal, based on orientation) offset of
the footer logo from the screen edge. This provides flexibility for
OEM branding placement.
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat.
Change-Id: Ie3942d9eee07091286118ac488d1cc85ecc96c4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Currently, the overcurrent pin enum is only defined up to OC5. However,
PCH-H chips support up to OC7 according to the 100 and 200 Series PCH
datasheets [1][2].
[1] Intel document 332690
[2] Intel document 335192
Change-Id: Ie35612eeaed2196caccc514429c7d80f84cf09a8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88159
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This partially reverts commit 32ebaef73c
("mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE")
as google/brox board has moved away from the PAD_CFG_GPI_INT_SWAPPED
usage. The revert simply removes the PAD_CFG_GPI_INT_SWAPPED solution,
which is not used anywhere anymore.
PAD_CFG0_ROUTE_SWAPPED bit can not be found in any PCH datasheet nor
EDS. Furthermore, the definition conflicts with PAD_CFG0_NAFVWE_ENABLE
bit, which, on the contrary, is defined in the datasheets and PCH EDS.
The conflict results in boards printing:
"GPIO XX doesn't support APIC routing," (where XX is pad number)
for each pad having the NAFVWE bit set.
Currently, none of the boards use PAD_CFG0_ROUTE_SWAPPED bit, and due
to the bit field conflict I assume it was mistakenly added.
Change-Id: I71299c9729f294cfafaec02222ef01e96b575740
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87485
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit addresses an issue within the DMAR (DMA Remapping) table
configuration for Intel Panther Lake (PTL) SoC. Specifically, it
introduces telemetry support to the DRHC structure. In addition, the
unnecessary Dynamic Platform and Thermal Framework (DPTF) entry is
removed from the SATC structure, aligning with the BIOS Requirements.
For detailed specifications, refer to the 812562 PTL Firmware
Architecture Specification (FAS).
BUG=b:423943431
TEST=Boot Fatcat board to ALOS. Disassemble the DMAR table using 2023+
version of iasl and check the DMAR for the telemetry entry in the DRHC
structure. There should not be a DPTF entry in the SATC structure.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I289f2520e4449a6aa33f53040b6c8f66faa4f2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88136
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A need arose to perform power and performance analysis on various SoC
SKUs with Fast VMode enabled, which the current chipset data structure
does not allow.
This commit refactors the configuration of Fast VMode I_TRIP thresholds
for Voltage Regulator (VR) domains across different power limit
configurations in Pantherlake SoCs. Previously, the I_TRIP threshold
values were statically set for each VR domain, but now they are defined
within a two-dimensional array that considers various power limit
scenarios.
This commit adds the I_TRIP values for different Power Limit SKUs
currently operated on Fatcat devices.
As part of this commit, the following two changes are being undone
because the previous code structure is now incompatible and lacks
purpose:
- commit 4b765fdd98 ("mb/google/fatcat: Disable EnableFastVmode on
Panther Lake H SoC")
- commit 5d7e2b4c0c ("mb/google/fatcat: Disable VR settings on Panther
Lake H SoC")
Change-Id: Iff21a9b0b230e08b99e032400cbe0021b8a4af43
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit adds the relevant IDs to support new Panther Lake (PTL)
System on Chips (SoCs). The CPU profiles are aligned with the matching
definition from Panther Lake Firmware Support Package (FSP) revision
3144.01.
TEST=A Fatcat device with CPUID 0xc06c1 and MCH_ID 0xb003 booted with
the relevant information printed in corebot logs.
[DEBUG] CPU: ID c06c1, Pantherlake B0, ucode: 00000105
[DEBUG] MCH: device id b003 (rev 06) is Pantherlake U
[DEBUG] PCH: device id e401 (rev 01) is Pantherlake SOC-H SuperSKU
[DEBUG] IGD: device id b090 (rev 00) is Pantherlake-U GT2
Change-Id: I66efe51a94edfffc2546817d06a63a9c4b51aa81
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88130
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit introduces the configuration and enabling of Thermal Design
Current (TDC) settings for various Panther Lake (PTL) SKUs. TDC values
are essential for managing thermal constraints, specifying the maximum
allowable current for specific Voltage Regulator (VR) domains under
given power limit scenarios. This enhancement provides tailored power
management for different SKUs, extracted from the Power Map Document
(#813278) which the Firmware Support Package (FSP) is not aligned with.
It introduces a new enum `soc_intel_pantherlake_sku` to represent
various SKUs as the current `soc_intel_pantherlake_power_limits` does
not meet the need for TDC settings. `cpuid_to_ptl` is updated to include
SKU mapping.
The VR romstage FSP params function implements logic to read SKU
information based on PCI device ID and CPU TDP, ensuring accurate
configuration.
TEST=FSP logs confirm TDC enablement at the specified values on a Fatcat
device operating an H12Xe Panther Lake SoC.
Change-Id: I889d5f08b0c75b950e5a30d25d6a370cccd295aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit makes power limit helper functions accessible during
romstage by updating the Makefile to include `power_limit.c` for both
ramstage and romstage.
It also modifies a preprocessor directive to ensure
`variant_update_cpu_power_limits()` is not compiled in romstage as it is
only intended for late-in-the-boot usage and will not compile properly
in romstage.
This change enables power management configuration identification early
in the boot process, allowing for better control over power settings at
this stage.
TEST=Successfully compile the Fatcat board target.
Change-Id: Ibf4d85c71dd8963063ca014d151438b68ea918db
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous default value of 10 milliseconds is being updated to 50
milliseconds to comply with the latest guidelines (Panther Lake FSP
release 3144.01 CnviWifi.asl file).
TEST=Invoke the following set of acpidbg commands to verify that the
_RST method still reaches state 2.
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x2
Change-Id: I2b0236c17117d368c1ee98e56c4c1b6525d63e27
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Introduce a new ACPI field, "WFDL", to specify the Power Level Device
Reset (PLDR) delay for Wi-Fi operations. This replaces the previously
hardcoded delay value, allowing for easier adjustment and configuration
of the PLDR timing in the future. By utilizing a named field, this
change facilitates potential updates to delay configurations.
Change-Id: I0f243ccf404afb83554136a3a310a98d6100d8ff
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Align the ACPI code comments with the actual generated code for Wi-Fi
power resource management. This change enhances the maintainability and
readability of the code by ensuring that comments accurately reflect the
runtime SSDT code.
Change-Id: Ie33c716305251356a462b086fa8c61ec8d16c3cb
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88112
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The change introduces new Advanced Configuration and Power Interface
(ACPI) methods to handle Bluetooth device states, including status
checks and device reset procedures. Specifically, it adds a Power
Resource for Reset (_PRR) method and the associated power resources to
enable Operating System (OS)-level resets for Connectivity Integrated
(CNVi) Bluetooth devices as specified in Intel document
number 559910. This allows the OS to perform Bluetooth hardware recovery
in case of errors, ensuring compliance with Intel's standards. The Power
Resource ACPI code was adapted from Panther Lake (PTL) Firmware Support
Package (FSP) revision 3144.01.
The new ACPI Bluetooth code introduces the CNMT mutex, similar to the
USB Bluetooth ACPI code, to avoid simultaneous CNVi resets when
executing Wi-Fi and Bluetooth power resource _RST methods.
TEST=The following two use cases were verified using acpidbg on a Fatcat
device.
1. Test CNVi Bluetooth _RST() completion.
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x0
acpidbg -b 'evaluate \_SB.PCI0.CNVB.RSTT' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVB.RSTT 1' # 0x1
acpidbg -b 'evaluate \_SB.PCI0.CNVB.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x2
2. Test that CNVi Wi-Fi _RST calls CNVi Bluetooth CFLR method.
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x0
acpidbg -b 'evaluate \_SB.PCI0.CNVW.RSTT' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1' # 0x0
acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x1
Change-Id: I2389901faf4fad131bb7226e356b47f4b1a4ddac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit adds horizontal alignment support for splash screen
logos into the existing helper function `calculate_logo_coordinates()`.
Updated helper function determines the X-coordinate for
logo placement based on specified horizontal alignment (left, right,
or center).
The `soc_load_logo_by_coreboot()` function is updated to utilize this
helper for footer logo placement when the panel orientation is
rotated (`LB_FB_ORIENTATION_RIGHT_UP`, `LB_FB_ORIENTATION_LEFT_UP`,
or `LB_FB_ORIENTATION_BOTTOM_UP`).
A new enum, `fw_splash_horizontal_alignment`, is defined in
`intelblocks/cfg.h` to explicitly represent these horizontal alignment
options, complete with descriptive comments and ASCII art.
This enhancement provides greater flexibility in positioning splash
screen elements, especially useful for rotated displays (for the footer
firmware splash screen).
BUG=b:423591644
TEST=Able to rotate the firmware splash screen (including footer logo)
while using portrait panel.
Change-Id: I23ae6d06e1df9cad1b2907a5c02b619dc831d468
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88030
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refines the comments for the fw_splash_vertical_alignment
enum members in src/soc/intel/common/block/include/intelblocks/cfg.h.
The redundant enum member names (e.g., FW_SPLASH_VALIGNMENT_CENTER:)
have been removed from the start of each comment block. This makes
the comments cleaner and more direct, focusing on the explanation of
the alignment behavior rather than re-stating the enum member's name.
Change-Id: Ife7a39622df1981adc09db82fecb5adc72d52d8d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the bitmap handling in the FSP2.0 driver to
enhance flexibility. Previously, `fsp_convert_bmp_to_gop_blt()`
directly called `bmp_load_logo()`, tying it to specific, predefined
bitmaps like low-battery or OEM splash logos. This prevented its
use for dynamic bitmap files (e.g., brand logos) at runtime.
To address this, `fsp_convert_bmp_to_gop_blt()` no longer handles
bitmap loading. Instead, a new unified API,
`fsp_load_and_convert_bmp_to_gop_blt()`, is introduced for scenarios
where FSP needs to load and convert a bitmap in a single step
(e.g., via its entrypoint).
This change makes `fsp_convert_bmp_to_gop_blt()` a generic API capable
of converting any provided bitmap into a BLT buffer. SoC layers
(like Alder Lake, Meteor Lake, Panther Lake) can now explicitly load
bitmaps and then pass them to `fsp_convert_bmp_to_gop_blt()`, or use
the new `fsp_load_and_convert_bmp_to_gop_blt()` for combined
operations.
Before:
- `soc_load_logo_by_coreboot()` -> `fsp_convert_bmp_to_gop_blt()`
(loads logo internally)
- `soc_load_logo_by_fsp()` -> `fsp_convert_bmp_to_gop_blt()`
(loads logo internally)
**After:**
- `soc_load_logo_by_coreboot()` -> loads logo
-> `fsp_convert_bmp_to_gop_blt()`
- `soc_load_logo_by_fsp()` -> `fsp_load_and_convert_bmp_to_gop_blt()`
BUG=b:423591644
TEST=Able to build and boot google/fatcat. FW splash screen looks
proper.
Change-Id: Ia20e8d42bca6f40c4eb652eb69e3fce84409fc35
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88014
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces PCI device details specific to Wildcat Lake
within the Panther Lake ACPI code, using conditional compilation
to differentiate configurations.
Key changes:
- Create separate ASL files for Panther Lake (`ptl_pcie.asl`) and
Wildcat Lake (`wcl_pcie.asl`) PCIe port configurations.
- Introduce conditional compilation to include Panther Lake or
Wildcat Lake ASL files.
- Wildcat Lake-specific changes compared to Panther Lake:
- Remove following
- PCIe RP : 00:1c.4 to 00:1c.7
: 00:06.2 & 00:06.3
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: I7f6c4f80a811c596824734d749b8d1c4864ccb9b
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88109
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit fixes a bug in the conditional logic for determining
Connectivity Integrated (CNVi) readiness in the `cnvw_fill_ssdt()`
function. The comparison previously checked if `LOCAL3_OP` was equal to
`1`, but it should instead verify if `LOCAL3_OP` equals
`CNVI_READY`. This adjustment ensures the accurate assessment of CNVI's
readiness state.
TEST=Running the following "acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1'",
"acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'" and "acpidbg -b
'evaluate \_SB.PCI0.CNVW.PRRS'" commands result in PRRS being read
as 2 (expected) instead of 1.
Change-Id: Ia6db833f3118e6975298aff4bd7c40657e4fcff7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88088
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Connectivity Integrated (CNVi) sideband port ID or Platform-Level
Device Reset (PLDR) register are specific to each SoC platform,
necessitating its relocation to respective SoC codebases. This change
enhances maintainability and readability by ensuring the port IDs are
defined within the context of the SoC they pertain to, removing
redundancy and potential misconfigurations across different SoCs.
Change-Id: I6ef1e077b8ffc076b7dc33ea90cc6ea92e819438
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88087
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enhance the readability and maintainability of the code by adding
detailed comments for the ACPI names "PRRS" and "RSTT" in the
`cnvw_fill_ssdt` function. These comments clarify the possible status
values for "PRRS" and the reset types for "RSTT", aiding developers in
understanding the function's logic and expected behavior.
Change-Id: I94486476cf2f95b8e1744ee369a9d9d6c734bba8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88086
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The commit leverages the \_SB.PCI0.BASE() ACPI method to remove the
hardcoded offset in the definition of the ACPI OperationRegion for CNVI
devices. Instead of using a fixed memory address addition, the code now
dynamically calculates the RegionOffset using the device's base address
(_ADR). This change enhances flexibility and adaptability for different
configurations and devices.
TEST=acpidbg -b 'evaluate \_SB.PCI0.CNVW.VDID' returns 0xE4408086 on a
Fatcat device.
Change-Id: Ia329aef0291c31862d002cb9bfa35930dab83fe5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The BASE method, previously located within USB Type-C Subsystem (TCSS)
ASL (ACPI Source Language) scope across multiple Intel System on Chip
(SoC) files, has been moved to the northbridge module. This refactoring
allows the BASE method to be utilized beyond the USB Type-C Subsystem
use-case.
The BASE method calculates the PCIe device base address using function
and device numbers.
Note: the BASE method is now under the \SB.PCI0 scope. It used to be
under the \_SB scope while only consumed by devices under the \SB.PCI0
scope.
TEST=On a Fatcat board, we verified that the BASE method returns
0xE00A3000 for the "./acpidbg -b 'evaluate \_SB.PCI0.BASE
0x140003'" command. We performed a non-regression test as well on
the TCSS DMA TDM0 device, which uses the BASE method, by verifying
that "./acpidbg -b 'evaluate \_SB.PCI0.TDM0.DMAD'" and "./acpidbg
-b 'evaluate \_SB.PCI0.TDM0.VDID'" return 0x22 and 0xE4338086,
respectively.
Change-Id: I431206e9f38a2a5695c90d4ae6d823fb231814aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch refactors `SPCO` ASL with helpers to remove macros.
1. Avoid inclusion of macros in ASL code.
2. Ensure runtime check can call appropriate clock routine either
for IOE die or PCH/SoC die.
This ensures runtime calls to correct clock routines for IOE,
PCH/SoC. Includes IOE PCR and IOE CLK ASL for compilation.
This inclusion increases the DSDT binary size by 250 bytes.
TEST=Able to build and boot google/fatcat.
w/ this patch:
```
fallback/dsdt.aml 0x94140 raw 25594 none
```
w/o this patch:
```
fallback/dsdt.aml 0x94140 raw 25350 none
```
Change-Id: Iee254e1766ca90662eb04548db26a408ce3c3d88
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87975
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rather than always enabling TME_KEY_REGENERATION_ON_WARM_BOOT, allow it
to be deselected but default to Y. Enabling it causes issues on boards
which use S3 suspend (vs S0ix), so allow it to be deselected so those
boards don't have to disable TME entirely.
TEST=build/boot starlabs/starbook_mtl, verify S3 resume works properly
with TME_KEY_REGENERATION_ON_WARM_BOOT deselected.
Change-Id: I60de19eddf7c2d8bc390b718b7cb1bf7d0267d47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88054
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
On the Fatcat board, the following ACPI error message was observed.
After applying the modification, the issue no longer appears.
ACPI error message via dmesg:
[ 0.209800] ACPI: Enabled 2 GPEs in block 00 to 7F
[ 0.210654] ACPI: \: Can't tag data node
[ 0.211039] ACPI: \: Can't tag data node
[ 0.211430] ACPI: \: Can't tag data node
[ 0.211672] ACPI: \: Can't tag data node
[ 0.212052] ACPI: \: Can't tag data node
BUG:None
TEST:Run 'dmesg | grep -i "Can't tag data node" -A 10 -B 10' and cannot see the error messages anymore.
Change-Id: I3da251b3c1950611fa0b4c125823f89d91dcd804
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Key changes:
- Updated ACPI southbridge configuration to include UFS support
for Wildcat Lake.
- Modified FSP parameters to enable UFS controllers for
Wildcat Lake.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: I3878b4a54a7be2565b37b0f885af5d55a6778795
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
SPI_BASE_ADDRESS is a fixed value to align with SoC and FSP usage.
Use Kconfig to define it so that SoC could override it per their needs.
Change-Id: If5e5338106deb18d108a70f5ffcd96dcb1e5e25a
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
fast_spi_cache_bios_region() refers to the SPI BAR before it is
initialized. Therefore, move the initialization before this function
to obtain the correct value.
If SPI is not initialized before use, an incorrect MTRR item is observed:
[DEBUG] 0x00000000fffff005: PHYBASE2: Address = 0x00000000fffff000, WP
[DEBUG] 0x000ffffffffff800: PHYMASK2: Length = 0x0000000000001000, Valid
TESTED=Build and boot on intel/avenuecity CRB, with below log:
[DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG] 0x000fffffff000800: PHYMASK2: Length = 0x0000000001000000, Valid
Change-Id: I8a755d2d18a567c09c5a66b03d4fdda5ba603133
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88046
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
The console UART base address for Panther Lake is being updated from
0xfe02c000 to 0xfe036000 (as per FSP version 3182). This correction
ensures the console initializes with the correct UART base address.
Additionally, now the UART base address is in sync between coreboot,
FSP and GFX PEIM.
BUG=b:423878608
TEST=Able to get FSP debug log while building google/fatcat.
```
dw-apb-uart.3: ttyS0 at MMIO 0xfe036000
```
Change-Id: I0caae8b5ea34561d88f5a4aa0cb12481db6f9417
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88073
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a mapping for the Core 3 N350 SoC, which has a MCH with PCI DID
0x4617, 8 efficiency cores, and a 7W TDP. This eliminates an error when
setting power limits due to the missing entry:
[ERROR] unknown SA ID: 0x4617, skipped power limits configuration
TEST=build/boot starlabs/starlite_adl with ADL-N Core 3 N350 SoC.
Change-Id: Ibd701ec5589a9a023a5538f470ff234a23249b45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Adds a new assignment in variant_update_cpu_power_limits() to enforce
the desired PL4 power limit regardless of whether Fast VMode is enabled
or not.
Change-Id: I8b376d283b2a28333c8efc932bc2f776dfb5584a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87958
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new power limit configuration for Fast VMode in
Panther Lake SoC. The changes include the addition of a
`tdp_pl4_fastvmode` field to the `soc_power_limits_config` structure,
allowing distinct PL4 power limit values when Fast VMode is enabled.
The values come from document #813278 Panther Lake H Power Map Rev 1.6.
Change-Id: I971d1aa7dd22a8135272577712283b4565810799
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87954
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The definitions added are based on the following reference documents:
1. Document #815002 Panther Lake H External Design Specification
Rev. 1.52
2. Document #813278 Panther Lake H Power Map Rev 1.6
Change-Id: I4545e0d48e49ac9a1c7df9b74384bf063455845c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87953
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
The tri-state power-on-after-failure options don't make sense
for all boards, so add a CFR option which allows for a simple
toggle for powering on after power loss
Change-Id: I7624f16f74c46b7b487da00d0ff669ff4c187dd6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a new CFR form to configure ASPM on CPU-attached PCIe root ports,
with the correct default and range of values for the associated UPD.
Adjust the verbiage on the existing ASPM CFR form so that it is clear
that form is used to configure PCH-attached root ports.
Change-Id: I73dd98fc09bf095da15cf4beb2c282e4c91400cd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Since the default ASPM UPD value (and valid values) differ between CPU
and PCH-attached root ports, add a new option variable for CPU-attached
RPs so that they are not inadvertently set to an invalid value, leading
ASPM to be disabled on those RPs.
Change-Id: I66ec77a3774a96cfe11f5827f5ba711ec826b236
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
ASPM_AUTO is not a valid value for the CpuPcieRpAspm[x] UPD; setting
it will result in the CPU root port having ASPM disabled by FSP.
Fix this by modifying aspm_control_to_upd() to take into account
whether it's being called for a PCH RP or a CPU RP, and setting
the default value appropriately.
TEST=build/boot starlabs/starfighter_rpl, verify CPU-attached RP
and downstream attached device have ASPM L1 enabled.
Change-Id: Ia89744fcae1294671061fb80be61b927a1578d4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87979
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the Pantherlake SOC code by leveraging existing
P2SB device operations, thereby removing redundant definitions. The
change eliminates unnecessary device operation structures (pcd_p2sb_ops
and pcd_p2sb_2_ops) and replaces them with references to already defined
operations (p2sb_ops and p2sb2_ops). This is similar to how it is
handled in the Alder Lake codebase.
BUG=b:422284273
TEST=Boot on Fatcat with and without this commit, compare the logs, and
verify that the I/O memory resources for P2SB and P2SB2 devices are
accounted for and are identical.
Change-Id: I9304b6aa16f07fdc7d927cc2e27879db549ac774
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87955
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Panther Lake H and U variants do not include any IOE die, making IOE
support unnecessary. This commit removes references to IOE support
across the Panther Lake SoC configuration and related files, simplifying
the codebase and avoiding potential misconfigurations.
These changes reduce unnecessary complexity and potential confusion
regarding IOE functionality in Panther Lake H and U SoCs, ensuring
configurations accurately reflect hardware capabilities.
BUG=b:422284273
Change-Id: I0ede4e1157c473763d53a9a3e6ab913ab470dc42
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87933
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit fixes memory corruption observed during stress
suspend-resume tests on the Fatcat board using Panther Lake U and H
SoCs. The issue stemmed from incorrect routing in the SPCO ACPI method
due to the use of SOC_INTEL_COMMON_BLOCK_IOE_P2SB, which was not
suitable as these SoCs lack an IOE die.
To address this, the commit switches from the IOE driver to the P2SB2
driver, aligning with the appropriate SOC_INTEL_COMMON_BLOCK_P2SB2
selection. The related function calls in the Panther Lake codebase have
been updated to use P2SB2-specific operations.
Panther Lake H and U SoC identifiers have been moved from the IOE driver
to the P2SB2 driver.
BUG=b:422284273
TEST=Memory corruption does not reproduce on the Fatcat board.
Change-Id: If678846b6285aea8cd53b0f7aebe3e75812a9330
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces a driver for a second P2SB (Primary to SideBand)
device to support certain Intel SoC configurations. The new driver
offers new functions, such as p2sb2_enable_bar(), p2sb2_sbi_read(), and
p2sb2_sbi_write(), for accessing and managing the second P2SB
interface (P2SB2). This interface is essential for managing sideband
communications in some Intel SoCs, such as Panther Lake.
BUG=b:422284273
TEST=Successful communication with the P2SB2 device during Fatcat board
boot.
Change-Id: I33941c85243e2529d1dd931b2afd7ab4814d9549
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit addresses a compilation error in the PCIe ClkReq SPCO method
due to incorrect conditional compilation logic. The previous
implementation lacked the necessary preprocessor directives to
differentiate between configurations when
SOC_INTEL_COMMON_BLOCK_IOE_P2SB is not defined.
BUG=b:422284273
Change-Id: Ie7b70babd279f7241f6e76113a6694a5bd0d782d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87930
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable POSTPONE_SPI_ACCESS to back up CMOS data and ELOG data in the
later boot phase to avoid flash access delay by another boot controller.
TEST=
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:120 (0 ms)
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I6b1b091dc60e6b20d39b90feebc8309306d6493e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Use POSTPONE_SPI_ACCESS to handle elog data later boot phase to avoid
flash access delay by other boot controllers.
Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU
firmwares. Boot-critical firmwares are loaded before CPU reset and
non-boot-critical firmwares are loaded during CPU boot. If another
controller accesses SPI to load firmwares, reading SPI by CPU is ok,
but writing to SPI for saving elog data can take ~32ms sometimes.
Saving elog data usually takes less than 1ms.
There are three elog handling sequences that need to move together
under the Kconfig:
- Soc folder
- Elog driver folder
- ChromeOS folder
Before this change, sometimes it delays like below:
BS: callback (0x7386d428) @ src/soc/intel/pantherlake/elog.c:216 (32 ms)
After this change, the delay is less than 1 ms:
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)
TEST
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms))
Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit updates the fill_tme_params() function to utilize the
CACHE_TMP_RAMTOP constant instead of hardcoded values for calculating
the TME exclusion range.
Change-Id: I199182de8b8b219b0c45b27746b7415527cb9976
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Enables CPU_SUPPORTS_INTEL_TME and TME_KEY_REGENERATION_ON_WARM_BOOT
for Panther Lake, providing hardware memory encryption capabilities.
TEST=Able to build and boot google/francka. Verified TME related
settings inside FSP are now enabled with this patch.
Change-Id: Iedc0d72d00e7e3c5b85916e2de4f020efd5ef024
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit moves the TME configuration into its own static function,
`fill_tme_params`, which is then called from
`fill_fspm_security_params`.
The `TME_KEY_REGENERATION_ON_WARM_BOOT` option is now supported,
allowing a new TME key to be generated on warm reboots.
This feature leverages the `SOC_INTEL_COMMON_BASECODE_RAMTOP`
configuration to determine a memory exclusion range for the new key.
Additionally, disable the `BIOS Guard` UPD as part of security FSP
UPD configuration.
TEST=Able to build and boot google/fatcat. S0ix also works with this
patch.
Change-Id: I1030a25262f1c3c24cf9f4886718689ee2c8155e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87808
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enhances the forced CSE sync mechanism by eliminating the
boot partition check for RO. It uses the persistent CMOS flags to
preserve the forced CSE update status across boots.
This patch also replaces the CSE status boolean variable with a bit
field to optimize CMOS memory utilization. Consequently, the remaining
bits can potentially be utilized for additional CSE states in future.
BUG=b:380220737
TEST=Verified forced CSE sync on google/rex0.
Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86153
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move `post_cpus_init` to execute at the entry of the `BS_DEV_ENABLE`
boot state. This function is responsible for synchronizing
and finalizing MTRR (Memory Type Range Registers) settings across all threads.
This change ensures that MTRR configuration occurs at the correct
point in the boot sequence:
- After main DRAM resources are determined and finalized (typically
by the `BS_DEV_RESERVE_RESOURCES` state). MTRRs define
attributes for these physical memory ranges.
Previously, `post_cpus_init` was hooked at `BS_WRITE_TABLES` (on exit)
or `BS_OS_RESUME` (on entry). Relocating to `BS_DEV_ENABLE` (on entry)
provides a more robust and correctly sequenced execution point for this
essential multi-processor (MP) MTRR setup.
BUG=b:413638298
TEST=Successfully built and booted google/fatcat. Verified that
MTRR programming, which depends on DRAM resource determination
(finalized by BS_DEV_RESERVE_RESOURCES), now correctly
executes at BS_DEV_ENABLE, prior to full device initialization.
Change-Id: I1d2b3f11e4ac268c5b35bf9a8062a77a48a0601a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update header files for FSP for Panther Lake platform to version
3144_01, with the previous version being 3071_00.
Changes include:
- Update UPD Offset in FspmUpd.h and FspsUpd.h.
- Update MemInfoHob.h:
- Update MEMORY_INFO_DATA_HOB, child structures and their data for
SMBIOS type 16/17 design change.
- Add new variable PprFailingChannelBitMask to
MEMORY_INFO_DATA_HOB.
- Update soc/intel/pantherlake/romstage/romstage.c: Refactor coreboot
to match MEMORY_INFO_DATA_HOB data structure.
BUG=b:414734316
TEST=Able to build google/fatcat. Verify that the updates to
MEMORY_INFO_DATA_HOB and its child structures for SMBIOS type 16/17
design changes are correctly integrated from FSP 3144_01 onwards.
Change-Id: I054e419ef23ada67347750e7a68014c2bb112199
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
