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soc/intel/pantherlake: Add Fast VMode PL4 Power Limit configuration

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This commit introduces a new power limit configuration for Fast VMode in
Panther Lake SoC. The changes include the addition of a
`tdp_pl4_fastvmode` field to the `soc_power_limits_config` structure,
allowing distinct PL4 power limit values when Fast VMode is enabled.

The values come from document #813278 Panther Lake H Power Map Rev 1.6.

Change-Id: I971d1aa7dd22a8135272577712283b4565810799
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87954
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2025-06-04 10:07:06 -07:00 • committed by Matt DeVillier
commit d9c5cef7f0
3 changed files with 15 additions and 3 deletions
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2
src/soc/intel/common/block/include/intelblocks/power_limit.h
View file

@ -32,6 +32,8 @@ struct soc_power_limits_config {
uint32_t tdp_psyspl3_dutycycle;
/* PL4 Value in Watts */
uint16_t tdp_pl4;
/* PL4 Value in Watts when Fast VMode is enabled */
uint16_t tdp_pl4_fastvmode;
/* Estimated maximum platform power in Watts */
uint16_t psys_pmax;
};

13
src/soc/intel/pantherlake/chipset_ptl.cb
View file

@ -2,24 +2,31 @@ chip soc/intel/pantherlake
device cpu_cluster 0 on end
# H404
register "power_limits_config[PTL_U_1_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 152,
.tdp_pl4 = 163,
.tdp_pl4_fastvmode = 150,
}"
# H204
register "power_limits_config[PTL_U_2_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 45,
.tdp_pl4 = 105,
.tdp_pl4_fastvmode = 95,
}"
# H12Xe and H484
register "power_limits_config[PTL_H_1_CORE]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 95,
.tdp_pl4 = 239,
.tdp_pl2_override = 64,
.tdp_pl4 = 175,
.tdp_pl4_fastvmode = 160,
}"
# H444
register "power_limits_config[PTL_H_2_CORE]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 64,

3
src/soc/intel/pantherlake/systemagent.c
View file

@ -171,6 +171,9 @@ static void configure_tdp(struct device *dev)
if (sa_pci_id == cpuid_to_ptl[i].cpu_id &&
tdp == cpuid_to_ptl[i].cpu_tdp) {
soc_config = &config->power_limits_config[cpuid_to_ptl[i].limits];
if (config->enable_fast_vmode[VR_DOMAIN_IA] &&
soc_config->tdp_pl4_fastvmode)
soc_config->tdp_pl4 = soc_config->tdp_pl4_fastvmode;
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
config_tdp = true;
printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n",