soc/intel/panterlake: avoid SPI access delay

Enable POSTPONE_SPI_ACCESS to back up CMOS data and ELOG data in the
later boot phase to avoid flash access delay by another boot controller.

TEST=
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:120 (0 ms)
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I6b1b091dc60e6b20d39b90feebc8309306d6493e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/soc/intel/pantherlake/Kconfig

@@ -13,6 +13,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
 	select DEFAULT_X2APIC_LATE_WORKAROUND
+	select POSTPONE_SPI_ACCESS
 	select DISPLAY_FSP_VERSION_INFO_2
 	select DRIVERS_USB_ACPI
 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW