soc/intel/pantherlake: Enable Thermal Design Current for various SKUs

This commit introduces the configuration and enabling of Thermal Design
Current (TDC) settings for various Panther Lake (PTL) SKUs. TDC values
are essential for managing thermal constraints, specifying the maximum
allowable current for specific Voltage Regulator (VR) domains under
given power limit scenarios. This enhancement provides tailored power
management for different SKUs, extracted from the Power Map Document
(#813278) which the Firmware Support Package (FSP) is not aligned with.

It introduces a new enum `soc_intel_pantherlake_sku` to represent
various SKUs as the current `soc_intel_pantherlake_power_limits` does
not meet the need for TDC settings. `cpuid_to_ptl` is updated to include
SKU mapping.

The VR romstage FSP params function implements logic to read SKU
information based on PCI device ID and CPU TDP, ensuring accurate
configuration.

TEST=FSP logs confirm TDC enablement at the specified values on a Fatcat
     device operating an H12Xe Panther Lake SoC.

Change-Id: I889d5f08b0c75b950e5a30d25d6a370cccd295aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/pantherlake/chip.h

@@ -68,18 +68,28 @@ enum soc_intel_pantherlake_cpu_tdps {
 	TDP_45W = 45,
 };
 
+enum soc_intel_pantherlake_sku {
+	PTL_H404_SKU,
+	PTL_H12XE_SKU,
+	PTL_H484_SKU,
+	PTL_H4XE_SKU,
+	PTL_H204_SKU,
+	MAX_PTL_SKUS
+};
+
 /* Mapping of different SKUs based on CPU ID and TDP values */
-static const struct {
+static const struct soc_intel_pantherlake_power_map {
 	unsigned int cpu_id;
 	enum soc_intel_pantherlake_power_limits limits;
 	enum soc_intel_pantherlake_cpu_tdps cpu_tdp;
+	enum soc_intel_pantherlake_sku sku;
 } cpuid_to_ptl[] = {
-	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W },
-	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W },
-	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W },
-	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W },
-	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W },
-	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W },
+	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W, PTL_H404_SKU },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W, PTL_H204_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W, PTL_H484_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
 };
 
 /* Types of display ports */
@@ -361,6 +371,23 @@ struct soc_intel_pantherlake_config {
 	 */
 	uint16_t ps_cur_3_threshold[NUM_VR_DOMAINS];
 
+	/*
+	 * Thermal Design Current (TDC) settings for various SKUs.
+	 *
+	 * This multidimensional array stores the Thermal Design Current (TDC)
+	 * values for different power limit configurations across multiple SKUs
+	 * and Voltage Regulator (VR) domains. TDC values indicate the maximum
+	 * allowable current for a given thermal configuration, which helps in
+	 * managing thermal constraints for each VR domain under specific power
+	 * limit scenarios.
+	 *
+	 * Each entry in the array is indexed by SKU and VR domain, providing
+	 * tailored TDC values for specific power management requirements.
+	 *
+	 * The TDC unit is defined 1/8A increments.
+	 */
+	uint16_t thermal_design_current[MAX_PTL_SKUS][NUM_VR_DOMAINS];
+
 	/*
 	 * SerialIO device mode selection:
 	 * PchSerialIoDisabled,

src/soc/intel/pantherlake/chipset_ptl.cb

@@ -9,6 +9,10 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 163,
 		.tdp_pl4_fastvmode = 150,
 	}"
+	register "thermal_design_current[PTL_H404_SKU]" = "{
+		[VR_DOMAIN_IA] = 34 * 8,
+		[VR_DOMAIN_GT] = 23 * 8
+	}"
 
 	# H204
 	register "power_limits_config[PTL_U_2_CORE]" = "{
@@ -17,6 +21,10 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 105,
 		.tdp_pl4_fastvmode = 95,
 	}"
+	register "thermal_design_current[PTL_H204_SKU]" = "{
+		[VR_DOMAIN_IA] = 23 * 8,
+		[VR_DOMAIN_GT] = 23 * 8
+	}"
 
 	# H12Xe and H484
 	register "power_limits_config[PTL_H_1_CORE]" = "{
@@ -25,8 +33,16 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 175,
 		.tdp_pl4_fastvmode = 160,
 	}"
+	register "thermal_design_current[PTL_H12XE_SKU]" = "{
+		[VR_DOMAIN_IA] = 39 * 8,
+		[VR_DOMAIN_GT] = 44 * 8
+	}"
+	register "thermal_design_current[PTL_H484_SKU]" = "{
+		[VR_DOMAIN_IA] = 39 * 8,
+		[VR_DOMAIN_GT] = 23 * 8
+	}"
 
-	# H444
+	# H4XE
 	register "power_limits_config[PTL_H_2_CORE]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 64,

src/soc/intel/pantherlake/romstage/fsp_params.c

@@ -3,6 +3,7 @@
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <device/pci.h>
 #include <elog.h>
 #include <fsp/debug.h>
 #include <fsp/fsp_debug_event.h>
@@ -303,6 +304,25 @@ static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->TccActivationOffset = config->tcc_offset;
 }
 
+static const struct soc_intel_pantherlake_power_map *get_map(const struct soc_intel_pantherlake_config *config)
+{
+	uint16_t sa_pci_id = pci_read_config16(PCI_DEVFN_ROOT, PCI_DEVICE_ID);
+	if (sa_pci_id == 0xffff) {
+		printk(BIOS_WARNING, "Unknown SA PCI Device!\n");
+		return NULL;
+	}
+
+	uint8_t tdp = get_cpu_tdp();
+	for (size_t i = 0; i < ARRAY_SIZE(cpuid_to_ptl); i++) {
+		const struct soc_intel_pantherlake_power_map *current = &cpuid_to_ptl[i];
+		if (current->cpu_id == sa_pci_id && current->cpu_tdp == tdp)
+			return current;
+	}
+
+	printk(BIOS_ERR, "Could not find the SKU power map\n");
+	return NULL;
+}
+
 static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 				       const struct soc_intel_pantherlake_config *config)
 {
@@ -315,6 +335,17 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 			}
 		}
 	}
+
+	const struct soc_intel_pantherlake_power_map *map = get_map(config);
+	if (!map)
+		return;
+
+	for (size_t i = 0; i < ARRAY_SIZE(config->thermal_design_current[0]); i++) {
+		if (!config->thermal_design_current[map->sku][i])
+			continue;
+		m_cfg->TdcEnable[i] = 1;
+		m_cfg->TdcCurrentLimit[i] = config->thermal_design_current[map->sku][i];
+	}
 }
 
 #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)