soc/intel/common/block/p2sb: Add driver for second P2SB device

This commit introduces a driver for a second P2SB (Primary to SideBand)
device to support certain Intel SoC configurations. The new driver
offers new functions, such as p2sb2_enable_bar(), p2sb2_sbi_read(), and
p2sb2_sbi_write(), for accessing and managing the second P2SB
interface (P2SB2). This interface is essential for managing sideband
communications in some Intel SoCs, such as Panther Lake.

BUG=b:422284273
TEST=Successful communication with the P2SB2 device during Fatcat board
     boot.

Change-Id: I33941c85243e2529d1dd931b2afd7ab4814d9549
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/soc/intel/common/block/include/intelblocks/p2sb.h

@@ -37,6 +37,14 @@ void ioe_p2sb_enable_bar(void);
 uint32_t ioe_p2sb_sbi_read(uint8_t pid, uint16_t reg);
 void ioe_p2sb_sbi_write(uint8_t pid, uint16_t reg, uint32_t val);
 
+/*
+ * Functions to access SoC P2SB2.
+ * pid argument: SBI port Id
+ */
+void p2sb2_enable_bar(void);
+uint32_t p2sb2_sbi_read(uint8_t pid, uint16_t reg);
+void p2sb2_sbi_write(uint8_t pid, uint16_t reg, uint32_t val);
+
 union p2sb_bdf {
 	struct {
 		uint16_t fn  : 3;

src/soc/intel/common/block/p2sb/Kconfig

@@ -12,6 +12,13 @@ config SOC_INTEL_COMMON_BLOCK_P2SB
 	help
 	  Intel Processor common P2SB driver for PCH or SoC die
 
+config SOC_INTEL_COMMON_BLOCK_P2SB2
+	bool
+	select SOC_INTEL_COMMON_BLOCK_BASE_P2SB
+	help
+	  Intel Processor common driver for a second P2SB (Primary to
+	  SideBand) interface to PCH or SoC die
+
 config SOC_INTEL_COMMON_BLOCK_IOE_P2SB
 	bool
 	select SOC_INTEL_COMMON_BLOCK_BASE_P2SB

src/soc/intel/common/block/p2sb/Makefile.mk

@@ -10,6 +10,12 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
 smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
 
+# p2sb2.c for SoC die P2SB2 IP
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB2) += p2sb2.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB2) += p2sb2.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB2) += p2sb2.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB2) += p2sb2.c
+
 # ioe_p2sb.c for IOE die P2SB IP
 bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOE_P2SB) += ioe_p2sb.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOE_P2SB) += ioe_p2sb.c

src/soc/intel/common/block/p2sb/p2sb2.c

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define __SIMPLE_DEVICE__
+
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/p2sb.h>
+#include <intelblocks/p2sblib.h>
+#include <intelblocks/pcr.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+
+uint32_t p2sb2_sbi_read(uint8_t pid, uint16_t reg)
+{
+	return p2sb_dev_sbi_read(PCI_DEV_P2SB2, pid, reg);
+}
+
+void p2sb2_sbi_write(uint8_t pid, uint16_t reg, uint32_t val)
+{
+	p2sb_dev_sbi_write(PCI_DEV_P2SB2, pid, reg, val);
+}
+
+void p2sb2_enable_bar(void)
+{
+	p2sb_dev_enable_bar(PCI_DEV_P2SB2, P2SB2_BAR);
+}
+
+static void read_resources(struct device *dev)
+{
+	mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB2_BAR, P2SB2_SIZE);
+}
+
+struct device_operations p2sb2_ops = {
+	.read_resources   = read_resources,
+	.set_resources    = noop_set_resources,
+	.ops_pci          = &pci_dev_ops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_WCL_P2SB2,
+	PCI_DID_INTEL_PTL_H_P2SB2,
+	PCI_DID_INTEL_PTL_U_H_P2SB2,
+	0,
+};
+
+static const struct pci_driver p2sb2 __pci_driver = {
+	.ops     = &p2sb2_ops,
+	.vendor  = PCI_VID_INTEL,
+	.devices = pci_device_ids,
+};