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soc/intel/cmn/block/aspm: Use separate option variable for CPU RP

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Since the default ASPM UPD value (and valid values) differ between CPU
and PCH-attached root ports, add a new option variable for CPU-attached
RPs so that they are not inadvertently set to an invalid value, leading
ASPM to be disabled on those RPs.

Change-Id: I66ec77a3774a96cfe11f5827f5ba711ec826b236
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit is contained in:
Matt DeVillier 2025-06-06 12:04:09 -05:00 • committed by Sean Rhodes
commit 9f8e5ab661
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/common/block/aspm/aspm.c
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@ -120,7 +120,7 @@ void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg,
s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm;
s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm;
s_cfg->CpuPcieRpAspm[index] =
aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), true);
aspm_control_to_upd(get_uint_option("pciexp_aspm_cpu", rp_cfg->pcie_rp_aspm), true);
s_cfg->CpuPcieRpL1Substates[index] =
l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
}