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mb/google/fatcat: Disable VR settings on Panther Lake H SoC

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Introduce a new static function `disable_vr_settings_on_pantherlake_h()`
to disable Voltage Regulator (VR) settings when a Panther Lake H System
on Chip (SoC) is detected.

The existing VR configurations, introduced by commit d19dd192db
("mb/google/fatcat: Add PTL-U Fast VMode Voltage Regulator settings"),
are optimized for Panther Lake U SoC, which can cause performance issues
on Panther Lake H boards under stress due to the I_TRIP value being
lower than what the device could actually use. By disabling these
settings, the Firmware Support Package (FSP) falls back to default
values for the SoC, which are more suitable.

TEST=Observe the "Disabling VR settings on PTL-H" log during a boot test
     on a Panther Lake H variant.

Change-Id: Ifc371212259fa724425158ad9ebadebd30c81705
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jeremy Compostella 2025-04-21 12:03:05 -07:00 • committed by Matt DeVillier
commit 5d7e2b4c0c
1 changed files with 47 additions and 0 deletions
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47
src/mainboard/google/fatcat/romstage.c
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <device/pci_ops.h>
#include <fsp/api.h>
#include <soc/romstage.h>
#include <soc/soc_chip.h>
@ -22,6 +23,49 @@ __weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
/* Nothing to do */
}
static bool soc_is_pantherlake_h(void)
{
uint16_t mch_id = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
if (mch_id == 0xffff) {
printk(BIOS_ERR, "No matching PCI DID present\n");
return false;
}
/*
* Identify Panther Lake H by testing all Memory Controller Hub (MCH) IDs utilized on fatcat
* devices.
*/
switch (mch_id) {
case PCI_DID_INTEL_PTL_H_ID_1:
case PCI_DID_INTEL_PTL_H_ID_2:
case PCI_DID_INTEL_PTL_H_ID_3:
case PCI_DID_INTEL_PTL_H_ID_4:
return true;
default:
return false;
}
}
static void disable_vr_settings_on_pantherlake_h(FSP_M_CONFIG *m_cfg)
{
if (!soc_is_pantherlake_h())
return;
/*
* The board operates a Panther Lake H SoC; disable the PTL-U VR settings.
*
* The Voltage Regulator (VR) configurations supplied by the device tree are
* specifically adjusted for a Panther Lake U SoC, which is intended for fatcat board
* designs. When these settings are applied to a board equipped with a Panther Lake H
* SoC, it may experience performance problems under high-stress conditions. This is
* because the I_TRIP value is set lower than the device's actual capability.
*/
printk(BIOS_INFO, "Disabling VR settings on PTL-H.\n");
for (size_t i = 0; i < NUM_VR_DOMAINS; i++)
m_cfg->CepEnable[i] = false;
}
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
const struct pad_config *pads;
@ -40,6 +84,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
memcfg_init(memupd, mem_config, &spd_info, half_populated);
/* Override FSP-M Voltage Regulator settings on Panther Lake H. */
disable_vr_settings_on_pantherlake_h(&memupd->FspmConfig);
/* Override FSP-M UPD per board if required. */
variant_update_soc_memory_init_params(memupd);
}