soc/intel/*/acpi: Move the BASE ACPI method to northbridge

The BASE method, previously located within USB Type-C Subsystem (TCSS)
ASL (ACPI Source Language) scope across multiple Intel System on Chip
(SoC) files, has been moved to the northbridge module. This refactoring
allows the BASE method to be utilized beyond the USB Type-C Subsystem
use-case.

The BASE method calculates the PCIe device base address using function
and device numbers.

Note: the BASE method is now under the \SB.PCI0 scope. It used to be
under the \_SB scope while only consumed by devices under the \SB.PCI0
scope.

TEST=On a Fatcat board, we verified that the BASE method returns
     0xE00A3000 for the "./acpidbg -b 'evaluate \_SB.PCI0.BASE
     0x140003'" command. We performed a non-regression test as well on
     the TCSS DMA TDM0 device, which uses the BASE method, by verifying
     that "./acpidbg -b 'evaluate \_SB.PCI0.TDM0.DMAD'" and "./acpidbg
     -b 'evaluate \_SB.PCI0.TDM0.VDID'" return 0x22 and 0xE4338086,
     respectively.

Change-Id: I431206e9f38a2a5695c90d4ae6d823fb231814aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/soc/intel/alderlake/acpi/tcss.asl

@@ -42,16 +42,6 @@
 
 Scope (\_SB)
 {
-	/* Device base address */
-	Method (BASE, 1)
-	{
-		Local0 = Arg0 & 0x7             /* Function number */
-		Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
-		Local2 = (Local0 << 12) + (Local1 << 15)
-		Local3 = \_SB.PCI0.GPCB() + Local2
-		Return (Local3)
-	}
-
 	/*
 	 * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
 	 * found in Device 31, Function 2, Offset 40h.

src/soc/intel/apollolake/acpi/northbridge.asl

@@ -131,5 +131,15 @@ Method (GPCB, 0, Serialized)
 	Return (Local0)
 }
 
+/* Device base address */
+Method (BASE, 1)
+{
+	Local0 = Arg0 & 0x7             /* Function number */
+	Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
+	Local2 = (Local0 << 12) + (Local1 << 15)
+	Local3 = \_SB.PCI0.GPCB() + Local2
+	Return (Local3)
+}
+
 /* GFX 00:02.0 */
 #include <drivers/intel/gma/acpi/gfx.asl>

src/soc/intel/common/block/acpi/acpi/northbridge.asl

@@ -277,6 +277,16 @@ Method (GDMB, 0, Serialized)
 	Return (Local0)
 }
 
+/* Device base address */
+Method (BASE, 1)
+{
+	Local0 = Arg0 & 0x7             /* Function number */
+	Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
+	Local2 = (Local0 << 12) + (Local1 << 15)
+	Local3 = \_SB.PCI0.GPCB() + Local2
+	Return (Local3)
+}
+
 /* PCI Device Resource Consumption */
 Device (PDRC)
 {

src/soc/intel/meteorlake/acpi/tcss.asl

@@ -42,16 +42,6 @@
 
 Scope (\_SB)
 {
-	/* Device base address */
-	Method (BASE, 1)
-	{
-		Local0 = Arg0 & 0x7             /* Function number */
-		Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
-		Local2 = (Local0 << 12) + (Local1 << 15)
-		Local3 = \_SB.PCI0.GPCB() + Local2
-		Return (Local3)
-	}
-
 	/*
 	 * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
 	 * found in Device 31, Function 2, Offset 40h.

src/soc/intel/pantherlake/acpi/tcss.asl

@@ -42,16 +42,6 @@
 
 Scope (\_SB)
 {
-	/* Device base address */
-	Method (BASE, 1)
-	{
-		Local0 = Arg0 & 0x7             /* Function number */
-		Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
-		Local2 = (Local0 << 12) + (Local1 << 15)
-		Local3 = \_SB.PCI0.GPCB() + Local2
-		Return (Local3)
-	}
-
 	/*
 	 * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
 	 * found in Device 31, Function 2, Offset 40h.

src/soc/intel/tigerlake/acpi/tcss.asl

@@ -42,16 +42,6 @@
 
 Scope (\_SB)
 {
-	/* Device base address */
-	Method (BASE, 1)
-	{
-		Local0 = Arg0 & 0x7             /* Function number */
-		Local1 = (Arg0 >> 16) & 0x1F    /* Device number */
-		Local2 = (Local0 << 12) + (Local1 << 15)
-		Local3 = \_SB.PCI0.GPCB() + Local2
-		Return (Local3)
-	}
-
 	/*
 	 * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
 	 * found in Device 31, Function 2, Offset 40h.