erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/cmn/block/cfr: Add CFR form for pciexp_aspm_cpu

Browse source 
Add a new CFR form to configure ASPM on CPU-attached PCIe root ports,
with the correct default and range of values for the associated UPD.
Adjust the verbiage on the existing ASPM CFR form so that it is clear
that form is used to configure PCH-attached root ports.

Change-Id: I73dd98fc09bf095da15cf4beb2c282e4c91400cd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit is contained in:
Matt DeVillier 2025-06-06 12:04:55 -05:00 • committed by Sean Rhodes
commit b3ac5ecdac
1 changed files with 18 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

20
src/soc/intel/common/block/include/intelblocks/cfr.h
View file

@ -44,10 +44,10 @@ static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
SM_ENUM_VALUE_END },
});
/* PCIe RP ASPM */
/* PCIe PCH RP ASPM */
static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
.opt_name = "pciexp_aspm",
.ui_name = "PCIe RP ASPM",
.ui_name = "PCIe PCH RP ASPM",
.ui_helptext = "Controls the Active State Power Management for PCIe devices."
" Enabling this feature can reduce power consumption of"
" PCIe-connected devices during idle times.",
@ -61,6 +61,22 @@ static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
SM_ENUM_VALUE_END },
});
/* PCIe CPU RP ASPM */
static const struct sm_object pciexp_aspm_cpu = SM_DECLARE_ENUM({
.opt_name = "pciexp_aspm_cpu",
.ui_name = "PCIe CPU RP ASPM",
.ui_helptext = "Controls the Active State Power Management for PCIe devices."
" Enabling this feature can reduce power consumption of"
" PCIe-connected devices during idle times.",
.default_value = ASPM_L0S_L1,
.values = (const struct sm_enum_value[]) {
{ "Disabled", ASPM_DISABLE },
{ "L0s", ASPM_L0S },
{ "L1", ASPM_L1 },
{ "L0sL1", ASPM_L0S_L1 },
SM_ENUM_VALUE_END },
});
/* PCIe Clock PM */
static const struct sm_object pciexp_clk_pm = SM_DECLARE_BOOL({
.opt_name = "pciexp_clk_pm",