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soc/intel/xeon_sp: Initialize SPI before using it

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fast_spi_cache_bios_region() refers to the SPI BAR before it is
initialized. Therefore, move the initialization before this function
to obtain the correct value.

If SPI is not initialized before use, an incorrect MTRR item is observed:
[DEBUG]  0x00000000fffff005: PHYBASE2: Address = 0x00000000fffff000, WP
[DEBUG]  0x000ffffffffff800: PHYMASK2: Length  = 0x0000000000001000, Valid

TESTED=Build and boot on intel/avenuecity CRB, with below log:
[DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG]  0x000fffffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid

Change-Id: I8a755d2d18a567c09c5a66b03d4fdda5ba603133
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88046
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit is contained in:
Jincheng Li 2025-05-15 14:43:49 +08:00 • committed by Matt DeVillier
commit ad05c65d72
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/xeon_sp/bootblock.c
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@ -73,6 +73,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
*/
assembly_timestamp = base_timestamp;
bootblock_timestamp = timestamp_get();
fast_spi_early_init(SPI_BASE_ADDRESS);
fast_spi_cache_bios_region();
bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp));
@ -80,7 +81,6 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
void bootblock_soc_early_init(void)
{
fast_spi_early_init(SPI_BASE_ADDRESS);
pch_enable_lpc();
/* Set up P2SB BAR. This is needed for PCR to work */