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soc/intel/cmn/block/aspm: Fix ASPM control for CPU root ports

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ASPM_AUTO is not a valid value for the CpuPcieRpAspm[x] UPD; setting
it will result in the CPU root port having ASPM disabled by FSP.
Fix this by modifying aspm_control_to_upd() to take into account
whether it's being called for a PCH RP or a CPU RP, and setting
the default value appropriately.

TEST=build/boot starlabs/starfighter_rpl, verify CPU-attached RP
and downstream attached device have ASPM L1 enabled.

Change-Id: Ia89744fcae1294671061fb80be61b927a1578d4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87979
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2025-06-06 11:55:21 -05:00 • committed by Sean Rhodes
commit 4247128e39
1 changed files with 5 additions and 5 deletions
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10
src/soc/intel/common/block/aspm/aspm.c
View file

@ -40,15 +40,15 @@
* +-------------------+--------------------------+-----------+-----------+
*/
static unsigned int aspm_control_to_upd(enum ASPM_control aspm_control)
static unsigned int aspm_control_to_upd(enum ASPM_control aspm_control, bool is_cpu_rp)
{
/* Disable without Kconfig selected */
if (!CONFIG(PCIEXP_ASPM))
return UPD_INDEX(ASPM_DISABLE);
/* Use auto unless overwritten */
/* Use default unless overwritten */
if (!aspm_control)
return UPD_INDEX(ASPM_AUTO);
return is_cpu_rp ? UPD_INDEX(ASPM_L0S_L1) : UPD_INDEX(ASPM_AUTO);
return UPD_INDEX(aspm_control);
}
@ -90,7 +90,7 @@ void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg,
s_cfg->PcieRpEnableCpm[index] =
get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM));
s_cfg->PcieRpAspm[index] =
aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm));
aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), false);
s_cfg->PcieRpL1Substates[index] =
l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
s_cfg->PcieRpPcieSpeed[index] =
@ -120,7 +120,7 @@ void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg,
s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm;
s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm;
s_cfg->CpuPcieRpAspm[index] =
aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm));
aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), true);
s_cfg->CpuPcieRpL1Substates[index] =
l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
}