soc/intel/common/block/cpu: Execute post_cpus_init at BS_DEV_ENABLE

Move `post_cpus_init` to execute at the entry of the `BS_DEV_ENABLE`
boot state. This function is responsible for synchronizing
and finalizing MTRR (Memory Type Range Registers) settings across all threads.

This change ensures that MTRR configuration occurs at the correct
point in the boot sequence:
-   After main DRAM resources are determined and finalized (typically
    by the `BS_DEV_RESERVE_RESOURCES` state). MTRRs define
    attributes for these physical memory ranges.

Previously, `post_cpus_init` was hooked at `BS_WRITE_TABLES` (on exit)
or `BS_OS_RESUME` (on entry). Relocating to `BS_DEV_ENABLE` (on entry)
provides a more robust and correctly sequenced execution point for this
essential multi-processor (MP) MTRR setup.

BUG=b:413638298
TEST=Successfully built and booted google/fatcat. Verified that
     MTRR programming, which depends on DRAM resource determination
     (finalized by BS_DEV_RESERVE_RESOURCES), now correctly
     executes at BS_DEV_ENABLE, prior to full device initialization.

Change-Id: I1d2b3f11e4ac268c5b35bf9a8062a77a48a0601a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

src/soc/intel/common/block/cpu/mp_init.c

@@ -233,5 +233,4 @@ static void post_cpus_init(void *unused)
 
 /* Do CPU MP Init before FSP Silicon Init */
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, coreboot_init_cpus, NULL);
-BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL);
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, post_cpus_init, NULL);
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, post_cpus_init, NULL);