soc/intel/pantherlake: Add support for the H204 SKU

The definitions added are based on the following reference documents:

1. Document #815002 Panther Lake H External Design Specification
   Rev. 1.52
2. Document #813278 Panther Lake H Power Map Rev 1.6

Change-Id: I4545e0d48e49ac9a1c7df9b74384bf063455845c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87953
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>

src/include/device/pci_ids.h

@@ -4556,6 +4556,7 @@
 #define PCI_DID_INTEL_LNL_M_ID			0x6400
 #define PCI_DID_INTEL_LNL_M_ID_1		0x6410
 #define PCI_DID_INTEL_PTL_U_ID_1		0xb000
+#define PCI_DID_INTEL_PTL_U_ID_2		0xb003
 #define PCI_DID_INTEL_PTL_H_ID_1		0xb001
 #define PCI_DID_INTEL_PTL_H_ID_2		0xb002
 #define PCI_DID_INTEL_PTL_H_ID_3		0xb004

src/soc/intel/common/block/systemagent/systemagent.c

@@ -428,6 +428,7 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_WCL_ID_1,
 	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_PTL_U_ID_1,
+	PCI_DID_INTEL_PTL_U_ID_2,
 	PCI_DID_INTEL_PTL_H_ID_1,
 	PCI_DID_INTEL_PTL_H_ID_2,
 	PCI_DID_INTEL_PTL_H_ID_3,

src/soc/intel/pantherlake/bootblock/report_platform.c

@@ -28,6 +28,7 @@ static struct {
 	const char *name;
 } mch_table[] = {
 	{ PCI_DID_INTEL_PTL_U_ID_1, "Pantherlake U" },
+	{ PCI_DID_INTEL_PTL_U_ID_2, "Pantherlake U" },
 	{ PCI_DID_INTEL_PTL_H_ID_1, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_2, "Pantherlake H" },
 	{ PCI_DID_INTEL_PTL_H_ID_3, "Pantherlake H" },

src/soc/intel/pantherlake/chip.h

@@ -54,6 +54,7 @@ enum soc_intel_pantherlake_sagv_gears {
 
 enum soc_intel_pantherlake_power_limits {
 	PTL_U_1_CORE,
+	PTL_U_2_CORE,
 	PTL_H_1_CORE,
 	PTL_H_2_CORE,
 	PTL_H_3_CORE,
@@ -74,6 +75,7 @@ static const struct {
 	enum soc_intel_pantherlake_cpu_tdps cpu_tdp;
 } cpuid_to_ptl[] = {
 	{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W },
+	{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W },
 	{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W },
 	{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W },
 	{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W },

src/soc/intel/pantherlake/chipset_ptl.cb

@@ -8,6 +8,12 @@ chip soc/intel/pantherlake
 		.tdp_pl4 = 152,
 	}"
 
+	register "power_limits_config[PTL_U_2_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 45,
+		.tdp_pl4 = 105,
+	}"
+
 	register "power_limits_config[PTL_H_1_CORE]" = "{
 		.tdp_pl1_override = 25,
 		.tdp_pl2_override = 95,