erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/pantherlake: Update CONSOLE_UART_BASE_ADDRESS Kconfig value

Browse source 
The console UART base address for Panther Lake is being updated from
0xfe02c000 to 0xfe036000 (as per FSP version 3182). This correction
ensures the console initializes with the correct UART base address.

Additionally, now the UART base address is in sync between coreboot,
FSP and GFX PEIM.

BUG=b:423878608
TEST=Able to get FSP debug log while building google/fatcat.

```
dw-apb-uart.3: ttyS0 at MMIO 0xfe036000
```
Change-Id: I0caae8b5ea34561d88f5a4aa0cb12481db6f9417
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88073
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2025-06-12 17:27:02 +05:30
commit 2ee72eaab1
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/soc/intel/pantherlake/Kconfig
View file

@ -308,7 +308,7 @@ config SOC_INTEL_USB3_DEV_MAX
config CONSOLE_UART_BASE_ADDRESS
hex
default 0xfe02c000
default 0xfe036000
depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate