soc/intel/cmn/acpi: Refactor SPCO ASL method
This patch refactors `SPCO` ASL with helpers to remove macros. 1. Avoid inclusion of macros in ASL code. 2. Ensure runtime check can call appropriate clock routine either for IOE die or PCH/SoC die. This ensures runtime calls to correct clock routines for IOE, PCH/SoC. Includes IOE PCR and IOE CLK ASL for compilation. This inclusion increases the DSDT binary size by 250 bytes. TEST=Able to build and boot google/fatcat. w/ this patch: ``` fallback/dsdt.aml 0x94140 raw 25594 none ``` w/o this patch: ``` fallback/dsdt.aml 0x94140 raw 25350 none ``` Change-Id: Iee254e1766ca90662eb04548db26a408ce3c3d88 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87975 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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3 changed files with 47 additions and 22 deletions
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@ -2,6 +2,9 @@
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#define PCR_BIOS_BUFFEN 0x8080
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/* IOE PCR access */
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#include <soc/intel/common/acpi/ioe_pcr.asl>
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Scope (\_SB)
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{
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/* MTL IOE CLK */
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@ -4,9 +4,33 @@
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#include <soc/intel/common/acpi/pch_clk.asl>
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/* IOE clock by P2SB */
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#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
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#include <soc/intel/common/acpi/ioe_clk.asl>
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#endif
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#include <soc/intel/common/acpi/ioe_clk.asl>
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/*
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* CLKM (Clock Manager): Helper Method to manage clock enable/disable
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* This method handles the enabling or disabling of clocks for either the
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* Integrated Controller (ICLK) or the IOE Die (ECLK) based on the provided
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* parameters.
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*
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* Arg0: Clock number
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* Arg1: Clock source, IOE Die Clock (1)/Integrated Controller Clock (0)
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* Arg2: Enable(1)/Disable(0) Clock
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*/
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Method (CLKM, 3, Serialized) {
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If (LEqual (Arg1, 1)) {
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If (LEqual (Arg2, 1)) {
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\_SB.ECLK.CLKE (Arg0)
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} Else {
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\_SB.ECLK.CLKD (Arg0)
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}
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} Else {
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If (LEqual (Arg2, 1)) {
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\_SB.ICLK.CLKE (Arg0)
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} Else {
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\_SB.ICLK.CLKD (Arg0)
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}
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}
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}
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/*
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* Configure PCIe ClkReq Override
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@ -14,25 +38,27 @@
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* Arg1: Enable(1)/Disable(0) Clock
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*/
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Method (SPCO, 2, Serialized) {
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#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
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If (LEqual (Arg1,1)) {
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If (LGreaterEqual (Arg0, CONFIG_IOE_DIE_CLOCK_START)) {
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\_SB.ECLK.CLKE (Subtract (Arg0, CONFIG_IOE_DIE_CLOCK_START))
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} Else {
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\_SB.ICLK.CLKE (Arg0)
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}
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} Else {
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If (LGreaterEqual (Arg0, CONFIG_IOE_DIE_CLOCK_START)) {
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\_SB.ECLK.CLKD (Subtract (Arg0, CONFIG_IOE_DIE_CLOCK_START))
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} Else {
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\_SB.ICLK.CLKD (Arg0)
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}
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/* Flag to indicate presence of IOE Die (1 = Present, 0 = Not Present) */
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Local0 = CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
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/* Clock start index */
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Local1 = 0
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/* Override clock start index if SOC_INTEL_COMMON_BLOCK_IOE_P2SB Kconfig is present. */
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If (LEqual (Local0, 1)) {
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Local1 = CONFIG_IOE_DIE_CLOCK_START
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}
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#else
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If (LEqual (Arg1,1)) {
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\_SB.ICLK.CLKE (Arg0)
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/* Clock number */
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Local2 = Arg0
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If (LGreaterEqual (Arg0, Local1)) {
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Local2 = Subtract (Arg0, Local1)
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} Else {
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\_SB.ICLK.CLKD (Arg0)
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/*
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* Override IOE die indicator if clock number is less than the IOE die clock
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* start index. Refer as clock number from non-IOE die.
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*/
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Local0 = 0;
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}
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#endif
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CLKM (Local2, Local0, Arg1)
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}
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@ -6,10 +6,6 @@
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/* SoC PCR access */
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#include <soc/intel/common/acpi/pch_pcr.asl>
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/* IOE PCR access */
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#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
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#include <soc/intel/common/acpi/ioe_pcr.asl>
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#endif
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/* PCIE src clock control */
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#include <soc/intel/common/acpi/pcie_clk.asl>
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