erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC

Browse source 
This commit addresses a performance issue on the Panther Lake H SoC by
disabling the EnableFastVmode setting in addition to the CepEnable
setting. It was discovered that merely disabling CepEnable was
insufficient, as the FSP continued to program Panther Lake U IccLimit on
FastVMode capable boards, causing performance degradation under
high-stress conditions. By also disabling EnableFastVmode, the I_TRIP
value is prevented from being set lower than the device's actual
capability.

TEST=Verify that IccLimit is programmed with FSP default values.

Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
This commit is contained in:
Jeremy Compostella 2025-04-30 15:06:36 -07:00 • committed by Jérémy Compostella
commit 4b765fdd98
1 changed files with 3 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/google/fatcat/romstage.c
View file

@ -62,8 +62,10 @@ static void disable_vr_settings_on_pantherlake_h(FSP_M_CONFIG *m_cfg)
* because the I_TRIP value is set lower than the device's actual capability.
*/
printk(BIOS_INFO, "Disabling VR settings on PTL-H.\n");
for (size_t i = 0; i < NUM_VR_DOMAINS; i++)
for (size_t i = 0; i < NUM_VR_DOMAINS; i++) {
m_cfg->CepEnable[i] = false;
m_cfg->EnableFastVmode[i] = false;
}
}
void mainboard_memory_init_params(FSPM_UPD *memupd)