The GPIO pad community definition for Skylake does not set the
pad_cfg_lock_offset member, leading to an "offset not defined for pad"
error when trying to lock a pad config in gpio_non_smm_lock_pad(). This
must be set to the offset of the first Pad Configuration Lock register
within each GPIO communities register blocks which can be found in the
GPIO sections of the processor I/O and PCH-H datasheets.
References:
Skylake-U/Y: Intel 332691
Sunrise Point-H: Intel 332996
Kaby Lake-U/Y: Intel 334659
Union Point-H: Intel 335193
Change-Id: I2991a7cbfb333d9fdda008cbb4cbc272aa508ef0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
According to EDS #872188, PTL-H484 has 8 more PCIe
lanes than PTL-H404 and 12Xe SKUs.
I believe there's been a mixup during bringup, as PCIe ACPI tables are
"gated" for an SKU with more PCIe 5.0 lanes.
To be exact, in a file: "src/soc/intel/pantherlake/acpi/ptl_pcie.asl"
we can notice PCIe 5.0 RootPorts depending on SOC_INTEL_PANTHERLAKE_H.
Google/Fatcat boards seem to be using PANTHERLAKE_U_H instead.
TEST: Build/boot intel/pantherlake_crb. Make sure Linux doesn't report
PCIe routing errors.
Change-Id: I1d136cf1959a3851d0ac37b256fd4df28a8d30df
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
protection
Add support for runtime control of BIOS lock
(BOOTMEDIA_SMM_BWP) via the CFR option API. This allows
users to enable/disable BIOS write protection in SMM
through the setup menu when explicitly enabled.
The implementation adds a new "bios_lock" CFR option that:
- Controls SMM BIOS write protection at runtime
- Sets EISS (Enable InSMM.STS) when enabled
- Enables SPI/LPC write protection in SMM
- Prevents unauthorised BIOS modifications outside SMM
Security model:
- Runtime control is opt-in via
BOOTMEDIA_SMM_BWP_RUNTIME_OPTION config
- When disabled, the option is suppressed in CFR
(not exposed in UI)
- Compile-time CONFIG(BOOTMEDIA_SMM_BWP) serves as the
default/fallback
- Protects against unauthorised EFI variable
modifications, bypassing BIOS lock when the runtime
option is not enabled
The option is integrated into Intel's common lockdown
code and SMI handlers, replacing compile-time-only
checks with conditional runtime lookups where
BOOTMEDIA_SMM_BWP_RUNTIME_OPTION is enabled.
Change-Id: Ie3b63462501e0d204c33dc3f8a006b73da0899d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89919
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the ModPHY settings are also available on other Intel platforms,
these parameters should be moved to common code.
Change-Id: Ic2666c7bbd576681dea7f360c396c068b42306e2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90943
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the first boot after coreboot is flashed, ABL FW performs
memory training and passes APOB data to coreboot. coreboot
writes APOB data in SPI flash along with hash of the APOB data.
If APOB signature is not written in CMOS, Memory context is
not restored by ABL in subsequent boot and full training is
initiated which increases boot time.coreboot keeps writing the
APOB data to flash in every boot due to hash mismatch of APOB
data which inturn increases boot time.This change fixes the
issue of ABL FW not doing Memory Context restore due to missing
CMOS signature.On some older platforms FSP writes this signature
unconditionally and hence this coreboot patch doesnt impact
the older platforms.
TEST= Validated on crater platform. APOB write is not initiated
by coreboot on every boot. APOB write to flash happens only once
after the coreboot flash.
Change-Id: Id799d0d2ed9f54e29db7681509f3d66c1638b6ac
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90947
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression introduced by commit d18cc50e6a ("soc/intel/xeon_sp:
Use common smm_relocate").
The MSR SMM_FEATURE_CONTROL_MSR is only implemented on client SoCs.
Starting from Haswell server onwards the "SMM feature control" on
server platforms resides on the UBOX in PCI space.
Parallel SMM relocation was never supported on server platforms, thus
disable parallel SMM relocation for now and thus fix booting on all
Xeon-SP platforms. Added a FIXME to possibly implement this feature
in the future.
TEST=Can boot on OCP/tiogapass again.
Change-Id: I7b4fbe633046acbf9f921cca722ff343a64962cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The generic Intel SMM S5 entry path disables all GPEs before asserting
SLP_EN, which clears OS-armed wake enables (e.g. LAN_WAKE) and prevents
Wake-on-LAN from S5.
Add a mainboard override hook, mainboard_smi_sleep_finalize(), called
after the S5 teardown but before SLP_EN is asserted, allowing boards to
restore required wake sources.
Change-Id: I9e97308ed94961fc4c08a10714b1b53f198bb593
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add USB port aliases to chipset_glk.cb and chipset_apl.cb to enable
boards to use device ref syntax for USB devices. Port counts match
hardware specs: GLK has 9 USB2/7 USB3 ports, APL has 8 USB2/7 USB3
ports.
Select 'DRIVERS_USB_ACPI' so that the required USB ACPI drivers are
built and linked for all boards.
Change-Id: Ibc7dd2cbfda8c8eb42b243ea7adcdb6d1fdea98b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Select SOC_INTEL_COMMON_BLOCK_ASPM and use the SoC common code for
programming PCIe root port power management. This adds programming of
PCIe RP clock PM and port speed, as well as allows for user override
via setup options for all fields. Remove the now-unused static methods
get_l1_substate_control() and get_aspm_control().
Additionally, check the port enable status before declaring the root
port config struct, to be consistent with ADL and MTL.
Change-Id: Ic30d714e609612ea46d34252c7c1d799652a9c2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90879
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SDXC device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from sd.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
SDXC controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ifee16988d0e5625a7b3c2be51ab70d2c8471747a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move CNVI WiFi device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them.
Remove corresponding DIDs from cnvi.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Remove the static declaration from cnvi_wifi_ops so the symbol is
exported and visible outside of cnvi.c.
This standardizes the approach across Intel SoCs and makes the
CNVI WiFi controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I82a2b20a8b967d1a3d5a80ae477def260c366be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90922
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move XDCI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from xdci.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
XDCI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ie8f8b5a952d072ecd1721bc8537734e85769b09d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move XHCI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from xhci.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
XHCI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I4a0551a0fc5a233153c62d5bb7b0b2f3596a81ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move HDA device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from hda.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Add 'Select SOC_INTEL_COMMON_BLOCK_HDA` to Apollolake/Geminilake
so those platforms can make use of the common driver. Since no
APL/GLK boards currently select `SOC_INTEL_COMMON_BLOCK_HDA_VERB`
the addition is a no-op.
This standardizes the approach across Intel SoCs and makes the
HDA controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common HDA driver code.
Change-Id: I0b3af4c2a441d4897341ee6c2cc5d75d70a6ebc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90919
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SMBUS device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from smbus.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
SMBUS controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I1c742836d923eb8f521bdbd7fa8260c82c1156ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move GSPI/SPI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from spi.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
GSPI/SPI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ia379cff36a5b277d89cad757edc094a5d786a51b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90917
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move UART device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from uart.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
UART controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Id26dad7997d64bcaad53fa39be23e52cb47dcc1d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90916
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SATA device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from sata.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Add `select SOC_INTEL_COMMON_BLOCK_SATA` to Apollolake SoC so that
the common block code is included, which it was not previously, even
though the APL/GLK PCI DIDs were included in the list. The net
effect is that the `SATA` ACPI device is now added to SSDT for
APL/GLK boards when they have SATA enabled.
This standardizes the approach across Intel SoCs and makes the
SATA controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I4c296a88c4da5f91d1039877ec858857496527f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move I2C device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from i2c.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
I2C controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common I2C driver code.
Change-Id: Ib68dd19c7c94d4cb6b41a1caf092b77f463c1c74
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90906
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Move PCIe root port operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from pcie.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files. Some of these
will be removed/cleaned up in subsequent patches.
This standardizes the approach across Intel SoCs and makes the
PCIe root port configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common PCIe driver code.
Change-Id: I8586b6efb8dbe164bc2a1d68b7131ffa22b00001
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Similar to other Intel SoCs, create a chipset.cb for Jasperlake
giving alias names to all known PCI devices. Taken from comments in
existing JSL board devicetrees, cross-referenced against the publicly
available JSL EDS.
At the same time, remove the usb2_lte device aliases in the BOTEN and
DRAWCIA dedede variants, and replace their references with the new
usb2_port4 alias, since we can only have a single alias per device.
TEST=build boten and drawcia dedede variants
Change-Id: I32552dbe0ab5305ea44b5e89432603884cf6589f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Commit ad6e3c847f ("tree: Drop Intel Ice Lake support") removed most
of the Ice Lake PCI IDs, but missed the ones with the ICP prefix
(Ice Point? Ice Lake Point?). Remove all PCI_DID_INTEL_ICP* defines
and references in common block drivers.
Change-Id: I9d33c69d174130aa781a00441fca367e0a67bcb4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90904
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add Turin OpenSIL driver and submodule pointing to turin_poc branch
of github.com/openSIL/openSIL repository.
Change-Id: Idd6d4e78a055926061de330da620c943b42a50a7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The current CBMEM top is situated at the base of 'dram_xbl_log'
(0x81A00000), leaving only 4.4MB of usable memory below it. This
space has become insufficient for the growing size requirements of
the coreboot configuration tables and boot services.
Relocate the CBMEM top to the base of the PIL region (0x866C0000).
This move increases the available contiguous memory for CBMEM
allocation from 4.4MB to 7.3MB, ensuring sufficient headroom for
the tables and reducing fragmentation for the OS and runtime services.
Changes:
- Update cbmem_top_chipset() to return _dram_pil as the new boundary.
- Update memlayout.ld documentation to reflect CBMEM's new position
directly below the PIL region.
TEST=Verified CBMEM initialization on Bluey; confirmed coreboot
tables are correctly allocated at the new high-memory boundary and
no overlaps occur with reserved regions.
Change-Id: I26d95b952634ce06ed2171c75bc6a129c15ec3b8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90912
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Fix the 4K alignment for PRERAM_DMA_COHERENT and adjust the post-RAM
memory layout to ensure page-aligned boundaries.
- Shift PRERAM_DMA_COHERENT from 0x14857000 to 0x14858000. This 4K
alignment is required for the MMU to correctly apply uncached
attributes without overlapping adjacent regions.
- Increase POSTRAM_STACK from 16K to 32K to provide more headroom
for complex ramstage operations.
- Shift and expand POSTRAM_DMA_COHERENT to 0x8000C000 (16K). This
ensures the coherent region starts on a 4K boundary after the
expanded stack, preventing cache coherency issues.
This alignment fix resolves intermittent SPI DMA failures and hash
mismatches observed when the DMA engine was handed unaligned
buffer addresses.
BUG=b:477842629
TEST=Verified successful boot on Bluey; confirmed SPI read
stability and vboot verification pass.
Change-Id: Ic5f813e4722d732c122186897abf845e4060db37
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90888
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boost the SPI bus clock frequency from 50MHz to 75MHz in the
bootblock early initialization.
This increase reduces the latency for loading subsequent stages
(romstage/ramstage) from the SPI flash. Since the QSPI core
can now be configured to 300MHz, this 75MHz bus speed
maintains a stable 1:4 integer divider ratio, ensuring optimal
signal integrity and timing margins for the flash interface.
BUG=b:478226455
TEST=Verified successful boot on Bluey. Observed a reduction (10ms)
in 'read SPI' duration in the console logs and confirmed that the
vboot hash verification passes consistently.
Change-Id: Idea0dbdd435cbbfe22a756d2b94b1cdfa3c70ffe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add a new frequency entry to the QSPI core clock configuration table
to support 75MHz (75 * 4 = 300MHz).
This is achieved by using the GPLL0 600MHz source with a divisor of 2.
Providing a 300MHz core clock allows for more granular control over
the physical bus speed (SCK). Specifically, it enables a stable 75MHz
SPI bus frequency via a clean 1/4 divider, which is an optimization
target for improving boot times on Bluey/Quenbi platforms.
BUG=b:478226455
TEST=Verified that 'clock_configure_qspi' can correctly look up and
set the 300MHz frequency in romstage.
Change-Id: I5320a68ff50a0d79daa2fc855b18b0f3ae819bbe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90886
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
This UPD is programmed for ADL, but not MTL and PTL. Add it to the
latter two so it functions as expected when set in devicetree for a
given PCIe root port.
TEST=build/boot Starlabs Starfighter MTL, verify Samsung NVMe drive
reliably detected in PCH-attached socket when timeout increased.
Change-Id: Iea744fed987d413c6487559005d668329a05fff4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Combine the size calculation and the CMDQ_SIZE_SEL bit setting into a
single write32 call for dsi->dsi_cmdq_size to optimize register access.
BUG=b:474187570
TEST=util/abuild/abuild -x -t GOOGLE_SKYWALKER -a --clean
BRANCH=skywalker
Change-Id: Idd08c8fab4120878c53fb94bf0e3cddb9a7eb513
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Also removes some dead code below which uses a dongle.py binary.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ia9b31a79f7637d31bbd824a8f6ad9137df429711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90818
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The other AMD SoCs already use the XHCI_GEVENT define and since it's
defined as GEVENT_31, this won't change the behavior.
Change-Id: I895f453497f6e03e1aff237ba6d6ec1ebecfaaaf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This patch adds Nova Lake specific device IDs to the header files and
driver-specific code.
Note: Device IDs D750h - D75Fh are intentionally omitted and will be
added in a future patch once validation is complete.
Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)
BUG=none
Change-Id: I00900c4f796b8bcc40f2bc09917172c71039c8a6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90748
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Intel development boards have SuperIO located at address 4e instead
of "default" 2e.
In order to correctly initialize the SIO/EC, we need to allow access to
that address in bootblock.
For further information refer to #854345 (Intel CNDA).
TEST: Build/boot intel/pantherlake_crb (out-of-tree, pending clearance).
Make sure that RS232 is working and SIO ACPI tables are correct.
Change-Id: I7944a48738fe0146cdf94635a01153a5d2331b24
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90854
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since Panther Lake, the FSP locks the TCC (Thermal Control Circuit) MSR
by default. However, Linux-based thermal management systems typically
configure this register from the operating system rather than the
firmware. Locking the TCC MSR in firmware prevents the OS from adjusting
thermal parameters as needed, potentially impacting system thermal
management and flexibility.
This commit explicitly sets the TccOffsetLock field to 0 in the FSP-M
configuration, ensuring that the TCC MSR remains unlocked after firmware
initialization.
BUG=b:474002582
TEST=MSR 0x1A2 is writable from the OS, as indicated by the successful
operation of
/sys/bus/pci/devices/0000:00:04/tcc_offset_degree_celsius on a
Fatcat device.
Change-Id: I445bc1408018d3de82919e46c8a368d93bbb1a77
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90718
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Some SoCs may require additional programming to get the SPI TPM
work properly. This hook is especially needed if mainboard selects
TPM_MEASURED_BOOT_INIT_BOOTBLOCK and TPM is initialized before any
vendor silicon initialization code runs (FSP or OpenSIL).
Change-Id: I90dbcbfb554ac3cfbcf23d708c3440d27959c632
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Update the SOC code based on the PPR for C1 stepping, doc 57238.
1. Turin CPU has less USB ports than Genoa, so the chip structure has
to reflect that. The number of ports has been reduced to match the
hardware capabilities.
2. Added early FCH initialization: legacy ISA devices, eSPI, I/O
decoding, UARTs, SMBus and SPI.
3. Updated AOAC device numbers.
4. Updated MMIO and I/O base addresses for CPU internal devices.
5. Added reserved RAM and MMIO reporting.
6. Adjusted root complex layout to match Turin IOHCs base addresses
and fabric IDs.
7. Extended chipset.cb devicetree to match the layout of devices on a
single socket Turin system.
Change-Id: I5272c1f2cd2aa259569d0bc6fa5c4073907b1673
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
ESPI1 MMIO is reported in ACPI already, but the resource allocator
must also know about it to avoid the allocation of resources in that
range.
TEST=Boot Gigabyte MZ33-AR1 and verify that ESPI1 address (0xfec30000)
is reported for PCI device 00:00.14.3 in coreboot logs:
dev: PCI: 00:00:14.3, index: 0x3, base: 0xfec30000, size: 0x1000
Change-Id: Ic4024e6aa37bd7568dcecbd7cae29be9ae587a7f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add API support to enable LPASS core clocks and vote for LP0 BCM
resource required for LPASS. This change includes support to enable
audio clocks.
LPASS is Low Power Audio Subsystem that runs audio and voice
processing on a dedicated DSP. This enables low-power audio operation
while the main CPUs remain in low-power states.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: If7684bee10d127866acac80e6aeefadaa177dc1f
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90851
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The MTE_TAG_ADDR macro is no longer used after the changes in CB:90144.
Remove the unused definition.
BUG=b:438666196
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a --clean
BRANCH=none
Change-Id: Ic71fa22292793162de882d3c764e7805301250c5
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The following error will be shown on non-NVMe SKUs.
[ERROR] DOMAIN: 00000000 missing read_resources
That's because when mainboard_needs_pcie_init() returns false, dev->ops
will be NULL, causing the '!curdev->ops || !curdev->ops->read_resources'
check to fail in device/device.c read_resources().
To prevent the misleading error message from showing up, for non-NVMe
SKUs, assign 'noop_domain_ops' to dev->ops.
BUG=none
TEST=emerge-tanjiro coreboot
BRANCH=rauru
Change-Id: If0f81aadda3fbde99f4df794cbdd885a607c9625
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90843
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This makes it runtime configurable; disabling it can save around
100ms boot time.
Change-Id: I9cddb07fc2e7caf754fa8d665249536c4885a4fe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89918
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
More complex systems, such as servers, have multiple IOMMUs. For
example, Turin CPUs have a total of 4 IOMMUs per socket. Abort IVHD
generation only if IOMMU is not present on domain 0. For other domains
simply continue the loop, so that other domains have their IOMMUs
described properly in the IVRS. To keep simple systems working as
before, IVHD generation is aborted, if IOMMU is not present in domain 0.
TEST=See IOMMUs on domains 1,3,4,6 being skipped during IVHD generation
instead of IVHD generation being aborted on domain 1 on
Gigabyte MZ33-AR1 console log.
Change-Id: Icd3a51621908dc3ee5c85aa1e5814f3b3ac69007
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89111
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On AMD glinda up to 3 CS# lines are available. Drive the correct
SPI flash chip select using register 0x1d when necessary. This
allows to modifiy the contents of the "backup" SPI flash when
booting from the primary SPI flash.
TEST=Can access backup SPI flash on AMD Glinda SoC.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I446ef54a27c7a29155948cef9219cdef7b52b776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The PSP can choose the SPI flash to boot from. One such case
would be a corrupted EFS or invalid PSP directory tables.
Read the active SPI CS index from register SPI_ALT_CS_REG and
use it in boot_device_spi_cs().
Register name is taken from Linux kernel.
TEST=Booted on AMD/glinda with EFS on SPI CS0 corrupted. Will
boot from SPI CS2 and log shows:
spi_init: Booting from SPI CS2
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2c806d4d1563aa2403e84dec9f8768081e5e208a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add verification to ensure that the integrated GPU is available,
avoiding crashes in FSP-M and FSP-S. The problem was first identified
on Skylake systems where the iGPU is missing or disabled, particularly
when VT-D is enabled, which can cause FSP-S to hang during boot.
Enabling SGX hides the issue, but it also leads to unstable
virtualization.
Apply the fix to Alderlake, Cannonlake, and Tigerlake SoCs in addition
to Skylake.
TEST=Build and boot to OS (Windows, Proxmox). Check to verify
functions work. (Skylake H110 + Xeon E3-1245 V5, E3-1260L V5,
i7-6700K, i3-7100)
Change-Id: I394f46ed5a277218a8dd587705eaecabe59fd110
Signed-off-by: Ulysse Ballesteros <ulysseballesteros@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89821
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Relocate the CBMEM top address from a hardcoded 0xC7800000 to the
start of the XBL log region (_dram_xbl_log).
This change moves the CBMEM region from the high Linux Kernel Reserve
block down into the lower DRAM Space 0, adjacent to other firmware
reserved regions. This consolidation prevents marking CBMEM range as
`reserved` and ensures CBMEM is placed in a more stable memory location
(marked available aka System RAM).
- Remove CBMEM_TOP define from addressmap.h.
- Update cbmem_top_chipset() to return (uintptr_t)_dram_xbl_log.
- Update memlayout.ld documentation to reflect the new memory map.
BUG=none
TEST=Boot on X1P42100 platform, verify CBMEM console and tables are
accessible and correctly located via 'cbmem -l'.
w/o this patch:
```
c7800000-cb7fffff : reserved
```
w/ this patch:
```
815a0000-819fffff : System RAM
```
Change-Id: I7392bb7a62d50640696301931940a7baa00351e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90760
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This reverts commit 292d7b9d3d.
The resume failure is caused by the improper DEVAPC setting in fsp_init
for DM/PM and SPM. If fsp_init runs prior to dpm_init and spm_init, it
requires AP to grant the access to DM/PM and SPM from DEVAPC. The fix is
done in CB:90756.
BUG=b:474254985
TEST=Run suspend/resume test
Change-Id: Id21327f6d65d31659cdb8b4bda3b0a0510c438e8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
