amdblock/lpc: Add SoC hook to set up SPI TPM decoding

Some SoCs may require additional programming to get the SPI TPM
work properly. This hook is especially needed if mainboard selects
TPM_MEASURED_BOOT_INIT_BOOTBLOCK and TPM is initialized before any
vendor silicon initialization code runs (FSP or OpenSIL).

Change-Id: I90dbcbfb554ac3cfbcf23d708c3440d27959c632
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>

src/soc/amd/common/block/include/amdblocks/lpc.h

@@ -140,6 +140,7 @@ void lpc_enable_sio_decode(const bool addr);
 uintptr_t lpc_spibase(void);
 void lpc_tpm_decode(void);
 void lpc_tpm_decode_spi(void);
+void soc_lpc_tpm_decode_spi(void);
 void lpc_enable_rom(void);
 void lpc_enable_spi_prefetch(void);
 uint32_t lpc_get_rom2_region(size_t *bios_size);

src/soc/amd/common/block/lpc/lpc_util.c

@@ -220,6 +220,8 @@ void lpc_tpm_decode(void)
 	pci_write_config32(_LPCB_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);
 }
 
+void __weak soc_lpc_tpm_decode_spi(void) { }
+
 /*
  * Enable FCH to decode TPM associated Memory and IO regions to SPI
  *
@@ -236,6 +238,8 @@ void lpc_tpm_decode_spi(void)
 					SPI_BASE_ADDRESS_REGISTER);
 	pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, spibase
 					| ROUTE_TPM_2_SPI);
+
+	soc_lpc_tpm_decode_spi();
 }
 
 /*