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soc/intel/pantherlake: Allow access to eSPI 4e address in bootblock

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Some Intel development boards have SuperIO located at address 4e instead
of "default" 2e.

In order to correctly initialize the SIO/EC, we need to allow access to
that address in bootblock.
For further information refer to #854345 (Intel CNDA).

TEST: Build/boot intel/pantherlake_crb (out-of-tree, pending clearance).
Make sure that RS232 is working and SIO ACPI tables are correct.

Change-Id: I7944a48738fe0146cdf94635a01153a5d2331b24
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90854
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Alicja Michalska 2026-01-21 18:05:10 +01:00 • committed by Matt DeVillier
commit cd8e9cd717
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/pantherlake/bootblock/pcd.c
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@ -48,8 +48,8 @@ static void pcd_die_config_pwrmbase(void)
static void pcd_die_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F |
LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
/* IO Decode Range */
if (CONFIG(DRIVERS_UART_8250IO))