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soc/amd/common/block/lpc: Report ESPI1 MMIO

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ESPI1 MMIO is reported in ACPI already, but the resource allocator
must also know about it to avoid the allocation of resources in that
range.

TEST=Boot Gigabyte MZ33-AR1 and verify that ESPI1 address (0xfec30000)
is reported for PCI device 00:00.14.3 in coreboot logs:
dev: PCI: 00:00:14.3, index: 0x3, base: 0xfec30000, size: 0x1000

Change-Id: Ic4024e6aa37bd7568dcecbd7cae29be9ae587a7f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Michał Żygowski 2026-01-21 15:19:32 +01:00
commit 56922d914b
2 changed files with 5 additions and 0 deletions
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1
src/soc/amd/common/block/include/amdblocks/espi.h
View file

@ -7,6 +7,7 @@
/* eSPI MMIO base lives at an offset of 0x10000 from the address in SPI BAR. */
#define ESPI_OFFSET_FROM_BAR 0x10000
#define ESPI1_OFFSET_FROM_BAR 0x20000
#define ESPI_DECODE 0x40
/* more bits defined in soc/common/amd/blocks/lpc/espi_def.h */

4
src/soc/amd/common/block/lpc/lpc.c
View file

@ -123,6 +123,10 @@ static void lpc_read_resources(struct device *dev)
/* Add a memory resource for the eSPI MMIO */
mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB);
/* Add a memory resource for the eSPI1 MMIO */
if (CONFIG(SOC_AMD_COMMON_BLOCK_HAS_ESPI1))
mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI1_OFFSET_FROM_BAR, 4 * KiB);
/* FCH IOAPIC */
mmio_range(dev, idx++, IO_APIC_ADDR, 4 * KiB);