soc/qualcomm/x1p42100: Add 75MHz configuration for QSPI core

Add a new frequency entry to the QSPI core clock configuration table
to support 75MHz (75 * 4 = 300MHz).

This is achieved by using the GPLL0 600MHz source with a divisor of 2.

Providing a 300MHz core clock allows for more granular control over
the physical bus speed (SCK). Specifically, it enables a stable 75MHz
SPI bus frequency via a clean 1/4 divider, which is an optimization
target for improving boot times on Bluey/Quenbi platforms.

BUG=b:478226455
TEST=Verified that 'clock_configure_qspi' can correctly look up and
set the 300MHz frequency in romstage.

Change-Id: I5320a68ff50a0d79daa2fc855b18b0f3ae819bbe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90886
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>

src/soc/qualcomm/x1p42100/clock.c

@@ -28,6 +28,11 @@ static struct clock_freq_config qspi_core_cfg[] = {
 		.src = SRC_GPLL0_MAIN_600MHZ,
 		.div = QCOM_CLOCK_DIV(3),
 	},
+	{
+		.hz = 300 * MHz,
+		.src = SRC_GPLL0_MAIN_600MHZ,
+		.div = QCOM_CLOCK_DIV(2),
+	},
 	{
 		.hz = 400 * MHz,
 		.src = SRC_GPLL0_MAIN_600MHZ,