Subrata Banik c31c194228 soc/qualcomm/x1p42100: Increase SPI bus frequency to 75MHz ... Boost the SPI bus clock frequency from 50MHz to 75MHz in the bootblock early initialization. This increase reduces the latency for loading subsequent stages (romstage/ramstage) from the SPI flash. Since the QSPI core can now be configured to 300MHz, this 75MHz bus speed maintains a stable 1:4 integer divider ratio, ensuring optimal signal integrity and timing margins for the flash interface. BUG=b:478226455 TEST=Verified successful boot on Bluey. Observed a reduction (10ms) in 'read SPI' duration in the console logs and confirmed that the vboot hash verification passes consistently. Change-Id: Idea0dbdd435cbbfe22a756d2b94b1cdfa3c70ffe Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>		2026-01-27 02:01:08 +00:00
..
amd	Makefile.mk: Remove "crt0" dead code	2026-01-25 19:05:42 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/{mtl,ptl}/fsp_params: Program PcieRpDetectTimeoutMs	2026-01-25 19:06:40 +00:00
mediatek	soc/mediatek/common: Combine dsi_cmdq_size register writes	2026-01-25 19:06:22 +00:00
nvidia	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
qualcomm	soc/qualcomm/x1p42100: Increase SPI bus frequency to 75MHz	2026-01-27 02:01:08 +00:00
rockchip	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
samsung
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx