soc/qualcomm/x1p42100: Align and expand DMA and stack regions

Fix the 4K alignment for PRERAM_DMA_COHERENT and adjust the post-RAM
memory layout to ensure page-aligned boundaries.

- Shift PRERAM_DMA_COHERENT from 0x14857000 to 0x14858000. This 4K
  alignment is required for the MMU to correctly apply uncached
  attributes without overlapping adjacent regions.
- Increase POSTRAM_STACK from 16K to 32K to provide more headroom
  for complex ramstage operations.
- Shift and expand POSTRAM_DMA_COHERENT to 0x8000C000 (16K). This
  ensures the coherent region starts on a 4K boundary after the
  expanded stack, preventing cache coherency issues.

This alignment fix resolves intermittent SPI DMA failures and hash
mismatches observed when the DMA engine was handed unaligned
buffer addresses.

BUG=b:477842629
TEST=Verified successful boot on Bluey; confirmed SPI read
stability and vboot verification pass.

Change-Id: Ic5f813e4722d732c122186897abf845e4060db37
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90888
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/qualcomm/x1p42100/memlayout.ld

@@ -215,7 +215,7 @@ SECTIONS
 	TTB(0x14842000, 56K)
 	PRERAM_STACK(0x14850000, 16K)
 	VBOOT2_WORK(0x14854000, 12K)
-	PRERAM_DMA_COHERENT(0x14857000, 8K)
+	PRERAM_DMA_COHERENT(0x14858000, 8K)
 	REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
 	CBFS_MCACHE(0x1485C000,16K)
 	FMAP_CACHE(0x14860400, 2K)
@@ -236,8 +236,8 @@ SECTIONS
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
-	POSTRAM_STACK(0x80000000, 16K)
-	POSTRAM_DMA_COHERENT(0x80004000, 8K)
+	POSTRAM_STACK(0x80000000, 32K)
+	POSTRAM_DMA_COHERENT(0x8000C000, 16K)
 	REGION(dram_ncc, 0x80A00000, 0x400000, 4K)
 	REGION(dram_cpucp, 0x80E00000, 0x7A0000, 4K)