soc/intel: Add Nova Lake device IDs

This patch adds Nova Lake specific device IDs to the header files and
driver-specific code.

Note: Device IDs D750h - D75Fh are intentionally omitted and will be
added in a future patch once validation is complete.

Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)

BUG=none

Change-Id: I00900c4f796b8bcc40f2bc09917172c71039c8a6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90748
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/drivers/intel/ish/ish.c

@@ -85,6 +85,7 @@ static const struct device_operations pci_ish_device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_ISHB,
 	PCI_DID_INTEL_WCL_ISHB,
 	PCI_DID_INTEL_PTL_H_ISHB,
 	PCI_DID_INTEL_PTL_U_H_ISHB,

src/drivers/intel/touch/touch.c

@@ -626,6 +626,10 @@ static const struct device_operations pci_thc_device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_THC0_1,
+	PCI_DID_INTEL_NVL_THC0_2,
+	PCI_DID_INTEL_NVL_THC1_1,
+	PCI_DID_INTEL_NVL_THC1_2,
 	PCI_DID_INTEL_MTL_THC0_SPI,
 	PCI_DID_INTEL_MTL_THC1_SPI,
 	PCI_DID_INTEL_PTL_U_H_THC0_I2C,

src/include/device/pci_ids.h

@@ -2190,6 +2190,7 @@
 #define PCI_DID_INTEL_PTL_H_ISHB	0xe445
 #define PCI_DID_INTEL_PTL_U_H_ISHB	0xe345
 #define PCI_DID_INTEL_WCL_ISHB		0x4d45
+#define PCI_DID_INTEL_NVL_ISHB		0xd354
 
 /* Intel 82371FB (PIIX) */
 #define PCI_DID_INTEL_82371FB_ISA		0x122e
@@ -3349,6 +3350,38 @@
 #define PCI_DID_INTEL_WCL_ESPI_29			0x4d1d
 #define PCI_DID_INTEL_WCL_ESPI_30			0x4d1e
 #define PCI_DID_INTEL_WCL_ESPI_31			0x4d1f
+#define PCI_DID_INTEL_NVL_ESPI_0			0xd300
+#define PCI_DID_INTEL_NVL_ESPI_1			0xd301
+#define PCI_DID_INTEL_NVL_ESPI_2			0xd302
+#define PCI_DID_INTEL_NVL_ESPI_3			0xd303
+#define PCI_DID_INTEL_NVL_ESPI_4			0xd304
+#define PCI_DID_INTEL_NVL_ESPI_5			0xd305
+#define PCI_DID_INTEL_NVL_ESPI_6			0xd306
+#define PCI_DID_INTEL_NVL_ESPI_7			0xd307
+#define PCI_DID_INTEL_NVL_ESPI_8			0xd308
+#define PCI_DID_INTEL_NVL_ESPI_9			0xd309
+#define PCI_DID_INTEL_NVL_ESPI_10			0xd30a
+#define PCI_DID_INTEL_NVL_ESPI_11			0xd30b
+#define PCI_DID_INTEL_NVL_ESPI_12			0xd30c
+#define PCI_DID_INTEL_NVL_ESPI_13			0xd30d
+#define PCI_DID_INTEL_NVL_ESPI_14			0xd30e
+#define PCI_DID_INTEL_NVL_ESPI_15			0xd30f
+#define PCI_DID_INTEL_NVL_ESPI_16			0xd310
+#define PCI_DID_INTEL_NVL_ESPI_17			0xd311
+#define PCI_DID_INTEL_NVL_ESPI_18			0xd312
+#define PCI_DID_INTEL_NVL_ESPI_19			0xd313
+#define PCI_DID_INTEL_NVL_ESPI_20			0xd314
+#define PCI_DID_INTEL_NVL_ESPI_21			0xd315
+#define PCI_DID_INTEL_NVL_ESPI_22			0xd316
+#define PCI_DID_INTEL_NVL_ESPI_23			0xd317
+#define PCI_DID_INTEL_NVL_ESPI_24			0xd318
+#define PCI_DID_INTEL_NVL_ESPI_25			0xd319
+#define PCI_DID_INTEL_NVL_ESPI_26			0xd31a
+#define PCI_DID_INTEL_NVL_ESPI_27			0xd31b
+#define PCI_DID_INTEL_NVL_ESPI_28			0xd31c
+#define PCI_DID_INTEL_NVL_ESPI_29			0xd31d
+#define PCI_DID_INTEL_NVL_ESPI_30			0xd31e
+#define PCI_DID_INTEL_NVL_ESPI_31			0xd31f
 
 /* Intel PCIE device ids  */
 #define PCI_DID_INTEL_LPT_H_PCIE_RP1			0x8c10
@@ -3829,6 +3862,21 @@
 #define PCI_DID_INTEL_WCL_PCIE_RP5                      0x4d61
 #define PCI_DID_INTEL_WCL_PCIE_RP6                      0x4d5c
 
+#define PCI_DID_INTEL_NVL_PCIE_RP1			0xd338
+#define PCI_DID_INTEL_NVL_PCIE_RP2			0xd339
+#define PCI_DID_INTEL_NVL_PCIE_RP3			0xd33a
+#define PCI_DID_INTEL_NVL_PCIE_RP4			0xd33b
+#define PCI_DID_INTEL_NVL_PCIE_RP5			0xd33c
+#define PCI_DID_INTEL_NVL_PCIE_RP6			0xd33d
+#define PCI_DID_INTEL_NVL_PCIE_RP7			0xd33e
+#define PCI_DID_INTEL_NVL_PCIE_RP8			0xd33f
+#define PCI_DID_INTEL_NVL_PCIE_RP9			0xd361
+#define PCI_DID_INTEL_NVL_PCIE_RP10			0xd35c
+#define PCI_DID_INTEL_NVL_PCIE_RP11			0xd365
+#define PCI_DID_INTEL_NVL_PCIE_RP12			0xd366
+#define PCI_DID_INTEL_NVL_PCIE_RP13			0xd367
+#define PCI_DID_INTEL_NVL_PCIE_RP14			0xd368
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3954,6 +4002,7 @@
 #define PCI_DID_INTEL_PTL_H_PMC			0xe421
 #define PCI_DID_INTEL_PTL_U_H_PMC		0xe321
 #define PCI_DID_INTEL_WCL_PMC			0x4d21
+#define PCI_DID_INTEL_NVL_PMC			0xd321
 
 /* Intel I2C device Ids */
 #define PCI_DID_INTEL_LPT_LP_I2C0		0x9c61
@@ -4119,6 +4168,13 @@
 #define PCI_DID_INTEL_WCL_I2C4			0x4d50
 #define PCI_DID_INTEL_WCL_I2C5			0x4d51
 
+#define PCI_DID_INTEL_NVL_I2C0			0xd378
+#define PCI_DID_INTEL_NVL_I2C1			0xd379
+#define PCI_DID_INTEL_NVL_I2C2			0xd37a
+#define PCI_DID_INTEL_NVL_I2C3			0xd37b
+#define PCI_DID_INTEL_NVL_I2C4			0xd350
+#define PCI_DID_INTEL_NVL_I2C5			0xd351
+
 /* Intel UART device Ids */
 #define PCI_DID_INTEL_LPT_LP_UART0		0x9c63
 #define PCI_DID_INTEL_LPT_LP_UART1		0x9c64
@@ -4222,6 +4278,10 @@
 #define PCI_DID_INTEL_WCL_UART1			0x4d26
 #define PCI_DID_INTEL_WCL_UART2			0x4d52
 
+#define PCI_DID_INTEL_NVL_UART0			0xd325
+#define PCI_DID_INTEL_NVL_UART1			0xd326
+#define PCI_DID_INTEL_NVL_UART2			0xd352
+
 /* Intel SPI device Ids */
 #define PCI_DID_INTEL_LPT_LP_GSPI0		0x9c65
 #define PCI_DID_INTEL_LPT_LP_GSPI1		0x9c66
@@ -4349,6 +4409,11 @@
 #define PCI_DID_INTEL_WCL_SPI1			0x4d30
 #define PCI_DID_INTEL_WCL_SPI2			0x4d46
 
+#define PCI_DID_INTEL_NVL_HWSEQ_SPI		0xd323
+#define PCI_DID_INTEL_NVL_SPI0			0xd327
+#define PCI_DID_INTEL_NVL_SPI1			0xd330
+#define PCI_DID_INTEL_NVL_SPI2			0xd347
+
 /* Intel IGD device Ids */
 #define PCI_DID_INTEL_SKL_GT1F_DT2			0x1902
 #define PCI_DID_INTEL_SKL_GT1_SULTM			0x1906
@@ -4522,6 +4587,11 @@
 #define PCI_DID_INTEL_PTL_H_GT2_4			0xb08f
 #define PCI_DID_INTEL_WCL_GT2_1				0xfd80
 #define PCI_DID_INTEL_WCL_GT2_2				0xfd81
+#define PCI_DID_INTEL_NVL_GT2_1				0xd741
+#define PCI_DID_INTEL_NVL_GT2_2				0xd742
+#define PCI_DID_INTEL_NVL_GT2_3				0xd743
+#define PCI_DID_INTEL_NVL_GT2_4				0xd744
+#define PCI_DID_INTEL_NVL_GT2_5				0xd745
 
 /* Intel Northbridge Ids */
 #define PCI_DID_INTEL_APL_NB			0x5af0
@@ -4691,6 +4761,11 @@
 #define PCI_DID_INTEL_WCL_ID_3			0xfd02
 #define PCI_DID_INTEL_WCL_ID_4			0xfd03
 #define PCI_DID_INTEL_WCL_ID_5			0xfd04
+#define PCI_DID_INTEL_NVL_ID_1			0xd701
+#define PCI_DID_INTEL_NVL_ID_2			0xd702
+#define PCI_DID_INTEL_NVL_ID_3			0xd704
+#define PCI_DID_INTEL_NVL_ID_4			0xd705
+#define PCI_DID_INTEL_NVL_ID_5			0xd70e
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
@@ -4777,6 +4852,8 @@
 #define PCI_DID_INTEL_SNR_XHCI			0x18d0
 #define PCI_DID_INTEL_WCL_XHCI			0x4d7d
 #define PCI_DID_INTEL_WCL_TCSS_XHCI		0x4d31
+#define PCI_DID_INTEL_NVL_XHCI			0xd37d
+#define PCI_DID_INTEL_NVL_TCSS_XHCI		0xd331
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4815,6 +4892,8 @@
 #define PCI_DID_INTEL_SNR_P2SB			0x18dd
 #define PCI_DID_INTEL_WCL_P2SB			0x4d20
 #define PCI_DID_INTEL_WCL_P2SB2			0x4d4c
+#define PCI_DID_INTEL_NVL_P2SB			0xd320
+#define PCI_DID_INTEL_NVL_P2SB2			0xd34c
 
 /* Intel SRAM device Ids */
 #define PCI_DID_INTEL_APL_SRAM			0x5aec
@@ -4836,6 +4915,7 @@
 #define PCI_DID_INTEL_PTL_H_SRAM		0xe47f
 #define PCI_DID_INTEL_PTL_U_H_SRAM		0xe37f
 #define PCI_DID_INTEL_WCL_SRAM			0x4d7f
+#define PCI_DID_INTEL_NVL_SRAM			0xd37e
 
 /* Intel AUDIO device Ids */
 #define PCI_DID_INTEL_LPT_H_AUDIO		0x8c20
@@ -4932,6 +5012,15 @@
 #define PCI_DID_INTEL_WCL_AUDIO_7		0x4d2e
 #define PCI_DID_INTEL_WCL_AUDIO_8		0x4d2f
 
+#define PCI_DID_INTEL_NVL_AUDIO_1		0xd328
+#define PCI_DID_INTEL_NVL_AUDIO_2		0xd329
+#define PCI_DID_INTEL_NVL_AUDIO_3		0xd32a
+#define PCI_DID_INTEL_NVL_AUDIO_4		0xd32b
+#define PCI_DID_INTEL_NVL_AUDIO_5		0xd32c
+#define PCI_DID_INTEL_NVL_AUDIO_6		0xd32d
+#define PCI_DID_INTEL_NVL_AUDIO_7		0xd32e
+#define PCI_DID_INTEL_NVL_AUDIO_8		0xd32f
+
 /* Intel HECI/ME device Ids */
 #define PCI_DID_INTEL_LPT_H_MEI			0x8c3a
 #define PCI_DID_INTEL_LPT_H_MEI_9		0x8cba
@@ -4989,6 +5078,7 @@
 #define PCI_DID_INTEL_PTL_U_H_CSE0		0xe370
 #define PCI_DID_INTEL_SNR_HECI1			0x18d3
 #define PCI_DID_INTEL_WCL_CSE0			0x4d70
+#define PCI_DID_INTEL_NVL_CSE0			0xd370
 
 /* Intel XDCI device Ids */
 #define PCI_DID_INTEL_APL_XDCI			0x5aaa
@@ -5017,6 +5107,7 @@
 #define PCI_DID_INTEL_PTL_H_XDCI		0xe47e
 #define PCI_DID_INTEL_PTL_U_H_XDCI		0xe37e
 #define PCI_DID_INTEL_WCL_XDCI		0x4d7e
+#define PCI_DID_INTEL_NVL_XDCI			0xd37f
 
 /* Intel SD device Ids */
 #define PCI_DID_INTEL_LPT_LP_SD			0x9c35
@@ -5078,6 +5169,7 @@
 #define PCI_DID_INTEL_PTL_TBT_DMA0		0xe433
 #define PCI_DID_INTEL_PTL_TBT_DMA1		0xe434
 #define PCI_DID_INTEL_WCL_TBT_DMA0		0x4d33
+#define PCI_DID_INTEL_NVL_TBT_DMA0		0xd333
 
 /* Intel WIFI Ids */
 #define PCI_DID_1000_SERIES_WIFI		0x0084
@@ -5120,6 +5212,7 @@
 #define PCI_DID_INTEL_RPL_IPU			0xa75d
 #define PCI_DID_INTEL_LNL_IPU			0x645d
 #define PCI_DID_INTEL_PTL_IPU			0xb05d
+#define PCI_DID_INTEL_NVL_IPU			0xd719
 
 /* Intel Dynamic Tuning Technology Device */
 #define PCI_DID_INTEL_CML_DTT			0x1903
@@ -5199,6 +5292,11 @@
 #define PCI_DID_INTEL_WCL_CNVI_WIFI_2		0x4d42
 #define PCI_DID_INTEL_WCL_CNVI_WIFI_3		0x4d43
 #define PCI_DID_INTEL_WCL_CNVI_BT		0x4d76
+#define PCI_DID_INTEL_NVL_CNVI_WIFI_0		0xd340
+#define PCI_DID_INTEL_NVL_CNVI_WIFI_1		0xd341
+#define PCI_DID_INTEL_NVL_CNVI_WIFI_2		0xd342
+#define PCI_DID_INTEL_NVL_CNVI_WIFI_3		0xd343
+#define PCI_DID_INTEL_NVL_CNVI_BT		0xd346
 
 /* Platform Security Engine */
 #define PCI_DID_INTEL_LNL_PSE0			0xa862
@@ -5224,6 +5322,7 @@
 #define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM		0x7a27
 #define PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM		0xb07d
 #define PCI_DID_INTEL_WCL_PUNIT_CRASHLOG_SRAM		0xfd7d
+#define PCI_DID_INTEL_NVL_PUNIT_CRASHLOG_SRAM		0xd70d
 
 /* Intel Trace Hub */
 #define PCI_DID_INTEL_MTL_TRACEHUB			0x7e24
@@ -5234,6 +5333,7 @@
 #define PCI_DID_INTEL_PTL_H_TRACEHUB			0xe424
 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB			0xe324
 #define PCI_DID_INTEL_WCL_TRACEHUB			0x4d24
+#define PCI_DID_INTEL_NVL_TRACEHUB			0xd324
 
 /* Intel Ethernet Controller device Ids */
 #define PCI_DID_INTEL_EHL_GBE_HOST		0x4B32
@@ -5265,6 +5365,10 @@
 #define PCI_DID_INTEL_ARP_S_THC0_2	0x7f59
 #define PCI_DID_INTEL_ARP_S_THC1_1	0x7f5a
 #define PCI_DID_INTEL_ARP_S_THC1_2	0x7f5b
+#define PCI_DID_INTEL_NVL_THC0_1	0xd348
+#define PCI_DID_INTEL_NVL_THC0_2	0xd349
+#define PCI_DID_INTEL_NVL_THC1_1	0xd34a
+#define PCI_DID_INTEL_NVL_THC1_2	0xd34b
 
 #define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291

src/soc/intel/common/block/cnvi/cnvi.c

@@ -473,6 +473,10 @@ static struct device_operations cnvi_wifi_ops = {
 };
 
 static const unsigned short wifi_pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_CNVI_WIFI_0,
+	PCI_DID_INTEL_NVL_CNVI_WIFI_1,
+	PCI_DID_INTEL_NVL_CNVI_WIFI_2,
+	PCI_DID_INTEL_NVL_CNVI_WIFI_3,
 	PCI_DID_INTEL_WCL_CNVI_WIFI_0,
 	PCI_DID_INTEL_WCL_CNVI_WIFI_1,
 	PCI_DID_INTEL_WCL_CNVI_WIFI_2,
@@ -858,6 +862,7 @@ static struct device_operations cnvi_bt_ops = {
 };
 
 static const unsigned short bt_pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_CNVI_BT,
 	PCI_DID_INTEL_WCL_CNVI_BT,
 	PCI_DID_INTEL_PTL_H_CNVI_BT,
 	PCI_DID_INTEL_PTL_U_H_CNVI_BT,

src/soc/intel/common/block/cse/cse.c

@@ -1527,6 +1527,7 @@ struct device_operations cse_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_CSE0,
 	PCI_DID_INTEL_WCL_CSE0,
 	PCI_DID_INTEL_PTL_H_CSE0,
 	PCI_DID_INTEL_PTL_U_H_CSE0,

src/soc/intel/common/block/dsp/dsp.c

@@ -14,6 +14,14 @@ static struct device_operations dsp_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_AUDIO_1,
+	PCI_DID_INTEL_NVL_AUDIO_2,
+	PCI_DID_INTEL_NVL_AUDIO_3,
+	PCI_DID_INTEL_NVL_AUDIO_4,
+	PCI_DID_INTEL_NVL_AUDIO_5,
+	PCI_DID_INTEL_NVL_AUDIO_6,
+	PCI_DID_INTEL_NVL_AUDIO_7,
+	PCI_DID_INTEL_NVL_AUDIO_8,
 	PCI_DID_INTEL_WCL_AUDIO_1,
 	PCI_DID_INTEL_WCL_AUDIO_2,
 	PCI_DID_INTEL_WCL_AUDIO_3,

src/soc/intel/common/block/graphics/graphics.c

@@ -361,6 +361,11 @@ const struct device_operations graphics_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_GT2_1,
+	PCI_DID_INTEL_NVL_GT2_2,
+	PCI_DID_INTEL_NVL_GT2_3,
+	PCI_DID_INTEL_NVL_GT2_4,
+	PCI_DID_INTEL_NVL_GT2_5,
 	PCI_DID_INTEL_WCL_GT2_1,
 	PCI_DID_INTEL_WCL_GT2_2,
 	PCI_DID_INTEL_PTL_U_GT2_1,

src/soc/intel/common/block/hda/hda.c

@@ -30,6 +30,14 @@ struct device_operations hda_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_AUDIO_1,
+	PCI_DID_INTEL_NVL_AUDIO_2,
+	PCI_DID_INTEL_NVL_AUDIO_3,
+	PCI_DID_INTEL_NVL_AUDIO_4,
+	PCI_DID_INTEL_NVL_AUDIO_5,
+	PCI_DID_INTEL_NVL_AUDIO_6,
+	PCI_DID_INTEL_NVL_AUDIO_7,
+	PCI_DID_INTEL_NVL_AUDIO_8,
 	PCI_DID_INTEL_WCL_AUDIO_1,
 	PCI_DID_INTEL_WCL_AUDIO_2,
 	PCI_DID_INTEL_WCL_AUDIO_3,

src/soc/intel/common/block/i2c/i2c.c

@@ -174,6 +174,12 @@ struct device_operations i2c_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_I2C0,
+	PCI_DID_INTEL_NVL_I2C1,
+	PCI_DID_INTEL_NVL_I2C2,
+	PCI_DID_INTEL_NVL_I2C3,
+	PCI_DID_INTEL_NVL_I2C4,
+	PCI_DID_INTEL_NVL_I2C5,
 	PCI_DID_INTEL_WCL_I2C0,
 	PCI_DID_INTEL_WCL_I2C1,
 	PCI_DID_INTEL_WCL_I2C2,

src/soc/intel/common/block/ipu/ipu.c

@@ -12,6 +12,7 @@ struct device_operations ipu_pci_ops = {
 };
 
 static const uint16_t pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_IPU,
 	PCI_DID_INTEL_PTL_IPU,
 	PCI_DID_INTEL_LNL_IPU,
 	PCI_DID_INTEL_RPL_IPU,

src/soc/intel/common/block/lpc/lpc.c

@@ -151,6 +151,38 @@ struct device_operations lpc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_ESPI_0,
+	PCI_DID_INTEL_NVL_ESPI_1,
+	PCI_DID_INTEL_NVL_ESPI_2,
+	PCI_DID_INTEL_NVL_ESPI_3,
+	PCI_DID_INTEL_NVL_ESPI_4,
+	PCI_DID_INTEL_NVL_ESPI_5,
+	PCI_DID_INTEL_NVL_ESPI_6,
+	PCI_DID_INTEL_NVL_ESPI_7,
+	PCI_DID_INTEL_NVL_ESPI_8,
+	PCI_DID_INTEL_NVL_ESPI_9,
+	PCI_DID_INTEL_NVL_ESPI_10,
+	PCI_DID_INTEL_NVL_ESPI_11,
+	PCI_DID_INTEL_NVL_ESPI_12,
+	PCI_DID_INTEL_NVL_ESPI_13,
+	PCI_DID_INTEL_NVL_ESPI_14,
+	PCI_DID_INTEL_NVL_ESPI_15,
+	PCI_DID_INTEL_NVL_ESPI_16,
+	PCI_DID_INTEL_NVL_ESPI_17,
+	PCI_DID_INTEL_NVL_ESPI_18,
+	PCI_DID_INTEL_NVL_ESPI_19,
+	PCI_DID_INTEL_NVL_ESPI_20,
+	PCI_DID_INTEL_NVL_ESPI_21,
+	PCI_DID_INTEL_NVL_ESPI_22,
+	PCI_DID_INTEL_NVL_ESPI_23,
+	PCI_DID_INTEL_NVL_ESPI_24,
+	PCI_DID_INTEL_NVL_ESPI_25,
+	PCI_DID_INTEL_NVL_ESPI_26,
+	PCI_DID_INTEL_NVL_ESPI_27,
+	PCI_DID_INTEL_NVL_ESPI_28,
+	PCI_DID_INTEL_NVL_ESPI_29,
+	PCI_DID_INTEL_NVL_ESPI_30,
+	PCI_DID_INTEL_NVL_ESPI_31,
 	PCI_DID_INTEL_WCL_ESPI_0,
 	PCI_DID_INTEL_WCL_ESPI_1,
 	PCI_DID_INTEL_WCL_ESPI_2,

src/soc/intel/common/block/p2sb/p2sb.c

@@ -145,6 +145,7 @@ const struct device_operations p2sb_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_P2SB,
 	PCI_DID_INTEL_WCL_P2SB,
 	PCI_DID_INTEL_PTL_H_P2SB,
 	PCI_DID_INTEL_PTL_U_H_P2SB,

src/soc/intel/common/block/p2sb/p2sb2.c

@@ -37,6 +37,7 @@ struct device_operations p2sb2_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_P2SB2,
 	PCI_DID_INTEL_WCL_P2SB2,
 	PCI_DID_INTEL_PTL_H_P2SB2,
 	PCI_DID_INTEL_PTL_U_H_P2SB2,

src/soc/intel/common/block/pcie/pcie.c

@@ -67,6 +67,20 @@ struct device_operations pcie_rp_ops = {
 };
 
 static const unsigned short pcie_device_ids[] = {
+	PCI_DID_INTEL_NVL_PCIE_RP1,
+	PCI_DID_INTEL_NVL_PCIE_RP2,
+	PCI_DID_INTEL_NVL_PCIE_RP3,
+	PCI_DID_INTEL_NVL_PCIE_RP4,
+	PCI_DID_INTEL_NVL_PCIE_RP5,
+	PCI_DID_INTEL_NVL_PCIE_RP6,
+	PCI_DID_INTEL_NVL_PCIE_RP7,
+	PCI_DID_INTEL_NVL_PCIE_RP8,
+	PCI_DID_INTEL_NVL_PCIE_RP9,
+	PCI_DID_INTEL_NVL_PCIE_RP10,
+	PCI_DID_INTEL_NVL_PCIE_RP11,
+	PCI_DID_INTEL_NVL_PCIE_RP12,
+	PCI_DID_INTEL_NVL_PCIE_RP13,
+	PCI_DID_INTEL_NVL_PCIE_RP14,
 	PCI_DID_INTEL_WCL_PCIE_RP1,
 	PCI_DID_INTEL_WCL_PCIE_RP2,
 	PCI_DID_INTEL_WCL_PCIE_RP3,

src/soc/intel/common/block/pmc/pmc.c

@@ -111,6 +111,7 @@ struct device_operations pmc_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_PMC,
 	PCI_DID_INTEL_WCL_PMC,
 	PCI_DID_INTEL_PTL_H_PMC,
 	PCI_DID_INTEL_PTL_U_H_PMC,

src/soc/intel/common/block/spi/spi.c

@@ -123,6 +123,10 @@ struct device_operations spi_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_HWSEQ_SPI,
+	PCI_DID_INTEL_NVL_SPI0,
+	PCI_DID_INTEL_NVL_SPI1,
+	PCI_DID_INTEL_NVL_SPI2,
 	PCI_DID_INTEL_WCL_HWSEQ_SPI,
 	PCI_DID_INTEL_WCL_SPI0,
 	PCI_DID_INTEL_WCL_SPI1,

src/soc/intel/common/block/sram/sram.c

@@ -33,6 +33,8 @@ static const struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_SRAM,
+	PCI_DID_INTEL_NVL_PUNIT_CRASHLOG_SRAM,
 	PCI_DID_INTEL_WCL_SRAM,
 	PCI_DID_INTEL_WCL_PUNIT_CRASHLOG_SRAM,
 	PCI_DID_INTEL_PTL_H_SRAM,

src/soc/intel/common/block/systemagent/systemagent.c

@@ -425,6 +425,11 @@ struct device_operations systemagent_ops = {
 };
 
 static const unsigned short systemagent_ids[] = {
+	PCI_DID_INTEL_NVL_ID_1,
+	PCI_DID_INTEL_NVL_ID_2,
+	PCI_DID_INTEL_NVL_ID_3,
+	PCI_DID_INTEL_NVL_ID_4,
+	PCI_DID_INTEL_NVL_ID_5,
 	PCI_DID_INTEL_WCL_ID_1,
 	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_WCL_ID_3,

src/soc/intel/common/block/tracehub/tracehub.c

@@ -42,6 +42,7 @@ static struct device_operations dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_TRACEHUB,
 	PCI_DID_INTEL_WCL_TRACEHUB,
 	PCI_DID_INTEL_PTL_H_TRACEHUB,
 	PCI_DID_INTEL_PTL_U_H_TRACEHUB,

src/soc/intel/common/block/uart/uart.c

@@ -308,6 +308,7 @@ static const char *uart_acpi_hid(const struct device *dev)
 static const char *uart_acpi_name(const struct device *dev)
 {
 	switch (dev->device) {
+	case PCI_DID_INTEL_NVL_UART0:
 	case PCI_DID_INTEL_WCL_UART0:
 	case PCI_DID_INTEL_PTL_H_UART0:
 	case PCI_DID_INTEL_PTL_U_H_UART0:
@@ -319,6 +320,7 @@ static const char *uart_acpi_name(const struct device *dev)
 	case PCI_DID_INTEL_SPT_H_UART0:
 	case PCI_DID_INTEL_CNP_H_UART0:
 		return "UAR0";
+	case PCI_DID_INTEL_NVL_UART1:
 	case PCI_DID_INTEL_WCL_UART1:
 	case PCI_DID_INTEL_PTL_H_UART1:
 	case PCI_DID_INTEL_PTL_U_H_UART1:
@@ -330,6 +332,7 @@ static const char *uart_acpi_name(const struct device *dev)
 	case PCI_DID_INTEL_SPT_H_UART1:
 	case PCI_DID_INTEL_CNP_H_UART1:
 		return "UAR1";
+	case PCI_DID_INTEL_NVL_UART2:
 	case PCI_DID_INTEL_WCL_UART2:
 	case PCI_DID_INTEL_PTL_H_UART2:
 	case PCI_DID_INTEL_PTL_U_H_UART2:
@@ -360,6 +363,9 @@ struct device_operations uart_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_UART0,
+	PCI_DID_INTEL_NVL_UART1,
+	PCI_DID_INTEL_NVL_UART2,
 	PCI_DID_INTEL_WCL_UART0,
 	PCI_DID_INTEL_WCL_UART1,
 	PCI_DID_INTEL_WCL_UART2,

src/soc/intel/common/block/usb4/usb4.c

@@ -52,6 +52,7 @@ static void tbt_dma_fill_ssdt(const struct device *dev)
 #endif
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_TBT_DMA0,
 	PCI_DID_INTEL_WCL_TBT_DMA0,
 	PCI_DID_INTEL_PTL_TBT_DMA0,
 	PCI_DID_INTEL_PTL_TBT_DMA1,

src/soc/intel/common/block/usb4/xhci.c

@@ -26,6 +26,7 @@ static struct device_operations usb4_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_TCSS_XHCI,
 	PCI_DID_INTEL_WCL_TCSS_XHCI,
 	PCI_DID_INTEL_PTL_H_TCSS_XHCI,
 	PCI_DID_INTEL_PTL_U_H_TCSS_XHCI,

src/soc/intel/common/block/xdci/xdci.c

@@ -28,6 +28,7 @@ struct device_operations usb_xdci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_XDCI,
 	PCI_DID_INTEL_WCL_XDCI,
 	PCI_DID_INTEL_PTL_H_XDCI,
 	PCI_DID_INTEL_PTL_U_H_XDCI,

src/soc/intel/common/block/xhci/xhci.c

@@ -131,6 +131,7 @@ struct device_operations usb_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_NVL_XHCI,
 	PCI_DID_INTEL_WCL_XHCI,
 	PCI_DID_INTEL_PTL_H_XHCI,
 	PCI_DID_INTEL_PTL_U_H_XHCI,