soc/qualcomm/x1p42100: Increase SPI bus frequency to 75MHz

Boost the SPI bus clock frequency from 50MHz to 75MHz in the
bootblock early initialization.

This increase reduces the latency for loading subsequent stages
(romstage/ramstage) from the SPI flash. Since the QSPI core
can now be configured to 300MHz, this 75MHz bus speed
maintains a stable 1:4 integer divider ratio, ensuring optimal
signal integrity and timing margins for the flash interface.

BUG=b:478226455
TEST=Verified successful boot on Bluey. Observed a reduction (10ms)
in 'read SPI' duration in the console logs and confirmed that the
vboot hash verification passes consistently.

Change-Id: Idea0dbdd435cbbfe22a756d2b94b1cdfa3c70ffe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>

src/soc/qualcomm/x1p42100/bootblock.c

@@ -5,7 +5,7 @@
 #include <soc/qspi_common.h>
 #include <soc/qupv3_config_common.h>
 
-#define SPI_BUS_CLOCK_FREQ (50 * MHz)
+#define SPI_BUS_CLOCK_FREQ (75 * MHz)
 
 void bootblock_soc_early_init(void)
 {