The console UART base address for Panther Lake is being updated from
0xfe02c000 to 0xfe036000 (as per FSP version 3182). This correction
ensures the console initializes with the correct UART base address.
Additionally, now the UART base address is in sync between coreboot,
FSP and GFX PEIM.
BUG=b:423878608
TEST=Able to get FSP debug log while building google/fatcat.
```
dw-apb-uart.3: ttyS0 at MMIO 0xfe036000
```
Change-Id: I0caae8b5ea34561d88f5a4aa0cb12481db6f9417
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88073
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since CB:84118 / 3d5ff65b27 (mb/google/cherry: Complete PCIe reset in
romstage) google-cherry mainboards do an early PERST# de-assert in
romstage. Since cherry does not have a pci_domain, `pci_root_bus()` will
return null, causing an assertion failure later in `find_dev_path()`.
Return if `pci_root_bus()` is NULL.
TEST=Successful boot on google/tomato
Change-Id: Icc35a53e38eef0088371592d8216ac74f9542166
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a mapping for the Core 3 N350 SoC, which has a MCH with PCI DID
0x4617, 8 efficiency cores, and a 7W TDP. This eliminates an error when
setting power limits due to the missing entry:
[ERROR] unknown SA ID: 0x4617, skipped power limits configuration
TEST=build/boot starlabs/starlite_adl with ADL-N Core 3 N350 SoC.
Change-Id: Ibd701ec5589a9a023a5538f470ff234a23249b45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Adds a new assignment in variant_update_cpu_power_limits() to enforce
the desired PL4 power limit regardless of whether Fast VMode is enabled
or not.
Change-Id: I8b376d283b2a28333c8efc932bc2f776dfb5584a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87958
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new power limit configuration for Fast VMode in
Panther Lake SoC. The changes include the addition of a
`tdp_pl4_fastvmode` field to the `soc_power_limits_config` structure,
allowing distinct PL4 power limit values when Fast VMode is enabled.
The values come from document #813278 Panther Lake H Power Map Rev 1.6.
Change-Id: I971d1aa7dd22a8135272577712283b4565810799
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87954
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The definitions added are based on the following reference documents:
1. Document #815002 Panther Lake H External Design Specification
Rev. 1.52
2. Document #813278 Panther Lake H Power Map Rev 1.6
Change-Id: I4545e0d48e49ac9a1c7df9b74384bf063455845c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87953
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
USB port 0 (P0) is force_suspended during the BootROM stage, and this
state won't be cleared in subsequent stages, causing P0 to become
unusable. Adding the P0 controller in coreboot ensures that the
force_suspended state is cleared, restoring P0 functionality. This
action requires setting the necessary register addresses, which is
handled by setup_usb_secondary_host().
BUG=b:417079837
BRANCH=None
TEST=Build passes and insert a USB device into USB port 0 can enumerate
the USB device.
Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I98534a833b344156a0e76e76ad7be88f98b2a967
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87977
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The tri-state power-on-after-failure options don't make sense
for all boards, so add a CFR option which allows for a simple
toggle for powering on after power loss
Change-Id: I7624f16f74c46b7b487da00d0ff669ff4c187dd6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a new CFR form to configure ASPM on CPU-attached PCIe root ports,
with the correct default and range of values for the associated UPD.
Adjust the verbiage on the existing ASPM CFR form so that it is clear
that form is used to configure PCH-attached root ports.
Change-Id: I73dd98fc09bf095da15cf4beb2c282e4c91400cd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Since the default ASPM UPD value (and valid values) differ between CPU
and PCH-attached root ports, add a new option variable for CPU-attached
RPs so that they are not inadvertently set to an invalid value, leading
ASPM to be disabled on those RPs.
Change-Id: I66ec77a3774a96cfe11f5827f5ba711ec826b236
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
ASPM_AUTO is not a valid value for the CpuPcieRpAspm[x] UPD; setting
it will result in the CPU root port having ASPM disabled by FSP.
Fix this by modifying aspm_control_to_upd() to take into account
whether it's being called for a PCH RP or a CPU RP, and setting
the default value appropriately.
TEST=build/boot starlabs/starfighter_rpl, verify CPU-attached RP
and downstream attached device have ASPM L1 enabled.
Change-Id: Ia89744fcae1294671061fb80be61b927a1578d4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87979
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enabling the mem_sub_sel and emi_n_sel MUXes in coreboot ensures proper
connectivity for multiple peripheral modules. Without these MUXes
enabled, some devices may experience communication failures or system
instability.
BUG=b:379008996
BRANCH=none
TEST=build pass and driver init ok.
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I3ee0432ac1f102343e49a51008b3ea552b3f2857
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87974
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit refactors the Pantherlake SOC code by leveraging existing
P2SB device operations, thereby removing redundant definitions. The
change eliminates unnecessary device operation structures (pcd_p2sb_ops
and pcd_p2sb_2_ops) and replaces them with references to already defined
operations (p2sb_ops and p2sb2_ops). This is similar to how it is
handled in the Alder Lake codebase.
BUG=b:422284273
TEST=Boot on Fatcat with and without this commit, compare the logs, and
verify that the I/O memory resources for P2SB and P2SB2 devices are
accounted for and are identical.
Change-Id: I9304b6aa16f07fdc7d927cc2e27879db549ac774
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87955
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Panther Lake H and U variants do not include any IOE die, making IOE
support unnecessary. This commit removes references to IOE support
across the Panther Lake SoC configuration and related files, simplifying
the codebase and avoiding potential misconfigurations.
These changes reduce unnecessary complexity and potential confusion
regarding IOE functionality in Panther Lake H and U SoCs, ensuring
configurations accurately reflect hardware capabilities.
BUG=b:422284273
Change-Id: I0ede4e1157c473763d53a9a3e6ab913ab470dc42
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87933
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit fixes memory corruption observed during stress
suspend-resume tests on the Fatcat board using Panther Lake U and H
SoCs. The issue stemmed from incorrect routing in the SPCO ACPI method
due to the use of SOC_INTEL_COMMON_BLOCK_IOE_P2SB, which was not
suitable as these SoCs lack an IOE die.
To address this, the commit switches from the IOE driver to the P2SB2
driver, aligning with the appropriate SOC_INTEL_COMMON_BLOCK_P2SB2
selection. The related function calls in the Panther Lake codebase have
been updated to use P2SB2-specific operations.
Panther Lake H and U SoC identifiers have been moved from the IOE driver
to the P2SB2 driver.
BUG=b:422284273
TEST=Memory corruption does not reproduce on the Fatcat board.
Change-Id: If678846b6285aea8cd53b0f7aebe3e75812a9330
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces a driver for a second P2SB (Primary to SideBand)
device to support certain Intel SoC configurations. The new driver
offers new functions, such as p2sb2_enable_bar(), p2sb2_sbi_read(), and
p2sb2_sbi_write(), for accessing and managing the second P2SB
interface (P2SB2). This interface is essential for managing sideband
communications in some Intel SoCs, such as Panther Lake.
BUG=b:422284273
TEST=Successful communication with the P2SB2 device during Fatcat board
boot.
Change-Id: I33941c85243e2529d1dd931b2afd7ab4814d9549
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit addresses a compilation error in the PCIe ClkReq SPCO method
due to incorrect conditional compilation logic. The previous
implementation lacked the necessary preprocessor directives to
differentiate between configurations when
SOC_INTEL_COMMON_BLOCK_IOE_P2SB is not defined.
BUG=b:422284273
Change-Id: Ie7b70babd279f7241f6e76113a6694a5bd0d782d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87930
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable POSTPONE_SPI_ACCESS to back up CMOS data and ELOG data in the
later boot phase to avoid flash access delay by another boot controller.
TEST=
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386f908) @ src/security/vboot/vbnv_cmos.c:120 (0 ms)
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I6b1b091dc60e6b20d39b90feebc8309306d6493e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Use POSTPONE_SPI_ACCESS to handle elog data later boot phase to avoid
flash access delay by other boot controllers.
Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU
firmwares. Boot-critical firmwares are loaded before CPU reset and
non-boot-critical firmwares are loaded during CPU boot. If another
controller accesses SPI to load firmwares, reading SPI by CPU is ok,
but writing to SPI for saving elog data can take ~32ms sometimes.
Saving elog data usually takes less than 1ms.
There are three elog handling sequences that need to move together
under the Kconfig:
- Soc folder
- Elog driver folder
- ChromeOS folder
Before this change, sometimes it delays like below:
BS: callback (0x7386d428) @ src/soc/intel/pantherlake/elog.c:216 (32 ms)
After this change, the delay is less than 1 ms:
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)
TEST
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms))
Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When using CONFIG_CONSOLE_SERIAL prevent the OS from putting the
debug uart into D3 state. In the D3 state it's not operating any
more, and the user cannot read debug messages on early kernel boot
or on shutdown any more.
For release builds CONFIG_CONSOLE_SERIAL should not be set and the
device can be put into powersave mode.
Change-Id: Id6b6a4d0a053a5e14e54cf623974376992f0abd8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The method for reading AUXDAC on mt8189 differs from previous methods.
To enhance code modularity and maintain compatibility, the differing
parts are moved to auxad_v1.h to supports legacy platforms.
BUG=b:379008996
BRANCH=none
TEST=emerge-geralt coreboot -j
Change-Id: Ib4bf0f593cab0480b7c78df7916f721f2e0833c7
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add the initialization code for CPU Dynamic Voltage and Frequency
Scaling (DVFS) for MCUPM.
BUG=b:410763782
BRANCH=none
TEST=Check the CPU frequencies are changing and not fixed values by
using the following commands in kernel:
1) set policy*/scaling_governor as "ondemand"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy0/scaling_governor"
"echo ondemand > /sys/devices/system/cpu/cpufreq/policy6/scaling_governor"
2) Check the CPU frequencies by repeating the command
"grep . /sys/devices/system/cpu/cpufreq/policy*/scaling_cur_freq"
The result is like
/sys/devices/system/cpu/cpufreq/policy0/scaling_cur_freq:650000
/sys/devices/system/cpu/cpufreq/policy6/scaling_cur_freq:2350000
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: I001d7a02d86892478b456f1c5ab3a6433434a19b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87916
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
To sync with the dramc_param_common.h change [1] from MediaTek's DRAM
blob, change the u32 config_dvfs field to u16 and add a new field
data_version. As all MediaTek SoCs using the structure are little endian
and currently only bit 0 is used for the config_dvfs field, this change
is backward compatible. Therefore, each SoC's DRAMC_PARAM_HEADER_VERSION
doesn't need to be bumped.
[1] commit a39b473a0a7d ("common/cros: Support storing data version in
full-k cached data")
FIXED=415715491
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: Ifcda7d360aefe083fc08c974e6dc62d1c9c12b5e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87912
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces initial support for PCI Express on the
Qualcomm x1p42100 SoC.
Key changes include:
- Selecting `CONFIG_PCI` in Kconfig to enable general PCI subsystem
support for this SoC.
- Selecting `CONFIG_NO_ECAM_MMCONF_SUPPORT`, indicating that this
platform will not use the standard MMCONFIG ECAM for PCI
configuration space access. An alternative mechanism will be required.
- Adding `../common/pcie_common.c` to the ramstage build if `CONFIG_PCI`
is enabled, incorporating common PCIe helper functions.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: I53e8bb3ce8551e8fa8c4b1cd39d89e12226c32f1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87858
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces `bootblock_soc_early_init` API for early SoC
initialization sequence in the bootblock.
- `bootblock_soc_early_init()`: This function now handles very early
initialization steps (before console init), specifically
`soc_mmu_init()` when the bootblock is not compressed.
- `bootblock_soc_init()`: This function retains the subsequent
initialization tasks including `clock_init()`, `quadspi_init()`,
and `qupv3_fw_init()`.
This change ensures MMU setup to occur before other peripheral and
clock initializations.
TEST=Able to get bootblock console log in proper.
Change-Id: I8bbcdb9c39e13fac81ef6a34647c4f343a619561
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87857
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit adds the `clock_init()` function for the Qualcomm x1p42100
SoC. This function is now called at the beginning of
`bootblock_soc_init()` to enable SoC-specific clock setup early in the
boot process.
The `clock_init()` function definition is currently a placeholder
and will be populated with the required clock configurations in
subsequent changes.
BUG=b:404985109
TEST=Able to build google/bluey
Change-Id: Ifb856ea4132def9cd3a36b081d24037a1a4efaba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87850
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the fill_tme_params() function to utilize the
CACHE_TMP_RAMTOP constant instead of hardcoded values for calculating
the TME exclusion range.
Change-Id: I199182de8b8b219b0c45b27746b7415527cb9976
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
BUG=b:379008996
BRANCH=none
TEST=build pass and run "storage init" in depthcharge shell on MTK EVB
firmware-shell: storage init
* 0: mtk_mmc
1 devices total
Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Change-Id: I82f2a155b810a8b9608d70fe0c015e6054d0be00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87862
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The MT8189 chipset comes in two variants: MT8189G and MT8189H. The
MT8189G variant uses a single PMIC IC (MT6315), whereas the MT8189H
variant uses two PMIC ICs. To ensure driver compatibility, we utilize
the CPU ID and segment ID to accurately determine the required number
of SPMIF instances.
BUG=b:379008996
BRANCH=none
TEST=build pass and boot up normally.
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I07bc21a2026803e76861b27a178d229deca2090a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87854
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
In some SoCs, such as MT8189G/H, different numbers of PMICs are
required. To ensure code reusability and compatibility, it is
necessary to dynamically set this variable. Therefore, spmi_dev_cnt
is changed to a function.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ib8d6306a81c276dceb021ddadec40803fd85019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87853
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To support the MTK firmware support package (FSP), reserve a 2MB region
in DRAM for loading `mtk_fsp_ramstage.elf` during ramstage.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If153d9746bea8c7faa8f9787029b44192c18899d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87813
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Enables CPU_SUPPORTS_INTEL_TME and TME_KEY_REGENERATION_ON_WARM_BOOT
for Panther Lake, providing hardware memory encryption capabilities.
TEST=Able to build and boot google/francka. Verified TME related
settings inside FSP are now enabled with this patch.
Change-Id: Iedc0d72d00e7e3c5b85916e2de4f020efd5ef024
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit moves the TME configuration into its own static function,
`fill_tme_params`, which is then called from
`fill_fspm_security_params`.
The `TME_KEY_REGENERATION_ON_WARM_BOOT` option is now supported,
allowing a new TME key to be generated on warm reboots.
This feature leverages the `SOC_INTEL_COMMON_BASECODE_RAMTOP`
configuration to determine a memory exclusion range for the new key.
Additionally, disable the `BIOS Guard` UPD as part of security FSP
UPD configuration.
TEST=Able to build and boot google/fatcat. S0ix also works with this
patch.
Change-Id: I1030a25262f1c3c24cf9f4886718689ee2c8155e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87808
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for VMODEM and VSRAM_MD buck converters in MT6359. These
buck converters are required for MT8189 to adjust voltage and CPU
frequency.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ifdf43748a139050ec9fba50f918e071dc622a670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87799
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently on power key long press, PMIC will be reset. It would cause
an unwanted reset pulse in the power-off sequence. To match expected
sequence, change PMIC behavior to "force shutdown".
BUG=b:395848137
BRANCH=none
TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse
Change-Id: Ia8fb9f4a1ffe05955fca51a58468ba338ef8e12d
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch enhances the forced CSE sync mechanism by eliminating the
boot partition check for RO. It uses the persistent CMOS flags to
preserve the forced CSE update status across boots.
This patch also replaces the CSE status boolean variable with a bit
field to optimize CMOS memory utilization. Consequently, the remaining
bits can potentially be utilized for additional CSE states in future.
BUG=b:380220737
TEST=Verified forced CSE sync on google/rex0.
Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86153
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Secure System Power Manager (SSPM) provides power control in secure
domain. The initialization flow is to load SSPM firmware to its SRAM
space and then enable it. It takes 19 ms to load sspm.bin.
coreboot logs:
CBFS: Found 'sspm.bin' @0x26740 size 0x645b in mcache @0xfffdd1ec
mtk_init_mcu: Loaded (and reset) sspm.bin in 19 msecs (59392 bytes)
BUG=b:379008996
BRANCH=none
TEST=build pass and see SSPM firmware loading log
Signed-off-by: Hailong Fan <hailong.fan@mediatek.corp-partner.google.com>
Change-Id: I9be0e7ee3d003b5ee9e07e4f136795755a11c5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87761
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MCUPM loader for mt8189.
It takes 36 ms to load mcupm.bin.
coreboot logs:
CBFS: Found 'mcupm.bin' @0x10d00 size 0x7fd6 in mcache @0xffffeb20
mtk_init_mcu: Loaded (and reset) mcupm.bin in 36 msecs (84124 bytes)
BUG=b:379008996
BRANCH=none
TEST=build pass and we can see the mcupm logs after reset releases.
Signed-off-by: Justin Yeh <justin.yeh@mediatek.corp-partner.google.com>
Change-Id: I4f3a4eb63d801df123e45f46fc715c39d858c377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87758
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Enabling MMCONF is simple and should be done first to allow bootblock
code to access the PCI config space. Required to cache ROM3 in
early_cache_setup() that is now called directly after enabling MMCONF.
Change-Id: I5d5f533258985211afafd9bf748f8e26f6128bd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86619
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On x86_64 use the ROM3 window to access the SPI flash. Use the
same mechanism as on Intel, where the lower 16Mbyte are mapped
using ROM2 window and the upper pages are mapped using the ROM3
window. By default the ROM3 window resides in high MMIO and thus
needs 1024GiB of the address space to be identity mapped in the
page tables.
This allows legacy 32-bit code to work on mappings in the lower
16MiB of the flash chip.
Introduces new messages in coreboot log:
[INFO ] ROM2 Decode Window: SPI flash base=0x0, Host base=0xff000000, Size=0x1000000
[INFO ] ROM3 Decode Window: SPI flash base=0x1000000, Host base=0xfd01000000, Size=0x3000000
TEST: Disabled ROM2 mapping and booted from ROM3 mapping in x86_64
on amd/birman+.
Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
When the number of eFuse reads exceeds a certain limit (with a maximum
of 20 million), a bit flip from 1 to 0 may happen. When that happens,
the bit flip will be automatically corrected by the eFuse hardware via
ECC (Error Correction Code), and the EFUSE_ECC_ERR register bit will be
set for the software to decide how to handle that.
Therefore, this patch adds a check for the EFUSE_ECC_ERR register bit.
If it's set due to a bit flip instead of a real error, we simply clear
it to avoid triggering a WDT reset.
BUG=b:379008996
BRANCH=none
TEST=build passed and check the WDT status debug log. This log is added
in local for test only.
[INFO ] mtk_wdt_clear_efuse_ecc: wdt_sta = 0x0
Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: Idd2763688c7ab6992a7c185e9e52b60bda88c94c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87744
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
