The console UART base address for Panther Lake is being updated from 0xfe02c000 to 0xfe036000 (as per FSP version 3182). This correction ensures the console initializes with the correct UART base address. Additionally, now the UART base address is in sync between coreboot, FSP and GFX PEIM. BUG=b:423878608 TEST=Able to get FSP debug log while building google/fatcat. ``` dw-apb-uart.3: ttyS0 at MMIO 0xfe036000 ``` Change-Id: I0caae8b5ea34561d88f5a4aa0cb12481db6f9417 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88073 Reviewed-by: <srinivas.kulkarni@intel.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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