soc/amd/common/block/lpc: Use ROM3 window if possible
On x86_64 use the ROM3 window to access the SPI flash. Use the
same mechanism as on Intel, where the lower 16Mbyte are mapped
using ROM2 window and the upper pages are mapped using the ROM3
window. By default the ROM3 window resides in high MMIO and thus
needs 1024GiB of the address space to be identity mapped in the
page tables.
This allows legacy 32-bit code to work on mappings in the lower
16MiB of the flash chip.
Introduces new messages in coreboot log:
[INFO ] ROM2 Decode Window: SPI flash base=0x0, Host base=0xff000000, Size=0x1000000
[INFO ] ROM3 Decode Window: SPI flash base=0x1000000, Host base=0xfd01000000, Size=0x3000000
TEST: Disabled ROM2 mapping and booted from ROM3 mapping in x86_64
on amd/birman+.
Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
This commit is contained in:
Patrick Rudolph
Matt DeVillier
parent
9d878fc6c0
commit
cbbf380fa4
4 changed files with 187 additions and 0 deletions
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@ -16,11 +16,29 @@ config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
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help
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Select this option to keep the 4 DWORD burst support enabled.
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config SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3
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bool
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default y if ROM_SIZE > 0x01000000
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depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE
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depends on !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
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depends on USE_X86_64_SUPPORT
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# Enable X86_CUSTOM_BOOTMEDIA because the fast SPI controller
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# driver provides a custom boot media device when multiple decode
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# windows are used for the BIOS region.
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select X86_CUSTOM_BOOTMEDIA
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help
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AMD specific SPI flash access. The lower 16MiB of the SPI flash are
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memory mapped on the ROM2 window and the upper SPI flash is mapped using
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the ROM3 window in high MMIO. The ROM3 window maps up to 64MiB of the
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SPI flash. The default address of ROM3 is below 1024GiB address boundary
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and thus can only be used in x86_64 mode.
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config SOC_AMD_COMMON_BLOCK_SPI_MMAP
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def_bool y
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select X86_CUSTOM_BOOTMEDIA
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depends on SOC_AMD_COMMON_BLOCK_SPI
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depends on !SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
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depends on !SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3
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help
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This option is required when CONFIG_ROM_SIZE is greater than 16 MiB.
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This flash driver still only mmaps 16 MiB of the flash (depending
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@ -4,6 +4,9 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y)
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all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP) += mmap_boot.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP) += mmap_boot.c
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all-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3) += mmap_boot_rom3.c
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smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3) += mmap_boot_rom3.c
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bootblock-y += fch_spi_ctrl.c
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romstage-y += fch_spi_ctrl.c
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verstage-y += fch_spi_ctrl.c
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163
src/soc/amd/common/block/spi/mmap_boot_rom3.c
Normal file
163
src/soc/amd/common/block/spi/mmap_boot_rom3.c
Normal file
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@ -0,0 +1,163 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boot_device.h>
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#include <spi_flash.h>
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#include <stdint.h>
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#include <amdblocks/lpc.h>
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enum window_type {
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/* Fixed decode window of max 16MiB size just below 4G boundary */
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ROM2_DECODE_WINDOW,
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/* Additional decode window for mapping BIOS region greater than 16MiB */
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ROM3_DECODE_WINDOW,
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TOTAL_DECODE_WINDOWS,
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};
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static struct xlate_region_device real_dev;
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static struct mem_region_device shadow_devs[TOTAL_DECODE_WINDOWS];
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static struct xlate_window real_dev_windows[TOTAL_DECODE_WINDOWS];
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static void initialize_window(const size_t win_idx, const enum window_type type,
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uintptr_t host_base, uintptr_t flash_base, size_t size)
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{
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mem_region_device_ro_init(&shadow_devs[win_idx], (void *)host_base, size);
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xlate_window_init(&real_dev_windows[win_idx], &shadow_devs[win_idx].rdev,
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flash_base, size);
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printk(BIOS_INFO, "ROM%d Decode Window: ",
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(type == ROM2_DECODE_WINDOW) ? 2 : 3);
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printk(BIOS_INFO, "SPI flash base=0x%lx, Host base=0x%lx, Size=0x%zx\n",
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flash_base, host_base, size);
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}
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/*
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*
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* Note: This configuration assumes no flash remapping (fch_spi_rom_remapping() = 0).
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*
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* +--------------+
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* | |
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* | |
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* | |
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* CONFIG_ROM_SIZE +------------+--------------------------+--------------------------------+- rom3_end
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* | | ^ | |
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* | | | | ROM3 |
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* | | | | |
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* | | | | |
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* | | + | |
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* | | rom3_size | |
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* | | + | |
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* | SPI ROM | | | |
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* | | +----+-----------------+--------------+
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* | | | | | |
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* | | | | | |
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* | | | V | |
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* | | | +---0xfd00000000--+--------------+- rom3_start
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* | | | | |
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* | | | | |
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* | | | | Other MMIO |
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* | | | | |
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* +------------+ --------------------+---------0x100000000--+--------------+- rom2_end
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* | | ^ | |
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* | | | | |
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* | | rom2_size | ROM2 |
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* | | | | |
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* | | V | |
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* 0 +------------+ ------------------------------0xFF0000000--+--------------+- rom2_start
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* | |
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* SPI flash | |
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* address | |
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* space | |
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* +--------------+
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*
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* Host address
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* space
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*/
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static void bios_mmap_init(void)
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{
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static bool init_done;
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size_t win_count = 0;
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size_t map_win_size = 0;
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if (init_done)
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return;
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/*
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* By default, fixed decode window (maximum size 16MiB) is mapped just
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* below the 4G boundary. This window maps the bottom part of the BIOS
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* region in the SPI flash address space to the host address space.
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*/
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size_t rom2_size = 0;
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const uintptr_t rom2_start = lpc_get_rom2_region(&rom2_size);
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if (rom2_start && rom2_size) {
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initialize_window(win_count, ROM2_DECODE_WINDOW, rom2_start, 0, rom2_size);
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win_count++;
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map_win_size += rom2_size;
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}
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/*
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* Remaining portion of the BIOS region up to a maximum of 64MiB is
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* mapped at the bottom of the ROM3 if the BIOS region is greater than 16MiB.
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* The ROM3 window is only used when it's inside the identity mapped
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* page tables used by x86_64.
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*
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* If the BIOS region is not greater than 16MiB, then the ROM3 window is not
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* enabled.
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*/
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size_t rom3_size;
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const uint64_t rom3_start = lpc_get_rom3_region(&rom3_size);
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const uint64_t rom3_end = rom3_start + rom3_size;
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if (CONFIG_ROM_SIZE > 16 * MiB) {
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assert(rom3_start);
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assert(rom3_size > 16 * MiB);
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assert(DIV_ROUND_UP(rom3_end, GiB) < CONFIG_CPU_PT_ROM_MAP_GB);
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}
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if (CONFIG_ROM_SIZE > 16 * MiB &&
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rom3_start > 0 &&
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rom3_size > 16 * MiB &&
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DIV_ROUND_UP(rom3_end, GiB) < CONFIG_CPU_PT_ROM_MAP_GB) {
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const size_t ext_win_size = MIN(rom3_size, CONFIG_ROM_SIZE - rom2_size);
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initialize_window(win_count, ROM3_DECODE_WINDOW,
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rom3_start + rom2_size, rom2_size, ext_win_size);
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win_count++;
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map_win_size += ext_win_size;
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}
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assert(map_win_size == CONFIG_ROM_SIZE);
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xlate_region_device_ro_init(&real_dev, win_count, real_dev_windows, map_win_size);
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init_done = true;
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}
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const struct region_device *boot_device_ro(void)
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{
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bios_mmap_init();
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return &real_dev.rdev;
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}
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uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table)
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{
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int i;
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uint32_t count = 0;
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bios_mmap_init();
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for (i = 0; i < TOTAL_DECODE_WINDOWS; i++) {
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if (region_sz(&real_dev_windows[i].sub_region) == 0)
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continue;
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count++;
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table->flash_base = region_offset(&real_dev_windows[i].sub_region);
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/* FIXME: Allow SPI mmap in 64-bit address space */
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if ((uintptr_t)rdev_mmap_full(&shadow_devs[i].rdev) < 4ULL * GiB)
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table->host_base = (uintptr_t)rdev_mmap_full(&shadow_devs[i].rdev);
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table->size = region_sz(&real_dev_windows[i].sub_region);
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table++;
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}
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return count;
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}
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@ -101,6 +101,9 @@ config CHIPSET_DEVICETREE
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string
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default "soc/amd/glinda/chipset.cb"
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config CPU_PT_ROM_MAP_GB
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default 1024
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config EARLY_RESERVED_DRAM_BASE
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hex
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default 0x2000000
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