soc/mediatek/mt8189: Add MCUPM loader
Add MCUPM loader for mt8189. It takes 36 ms to load mcupm.bin. coreboot logs: CBFS: Found 'mcupm.bin' @0x10d00 size 0x7fd6 in mcache @0xffffeb20 mtk_init_mcu: Loaded (and reset) mcupm.bin in 36 msecs (84124 bytes) BUG=b:379008996 BRANCH=none TEST=build pass and we can see the mcupm logs after reset releases. Signed-off-by: Justin Yeh <justin.yeh@mediatek.corp-partner.google.com> Change-Id: I4f3a4eb63d801df123e45f46fc715c39d858c377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87758 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Justin Yeh
Yidi Lin
parent
bc3af56fdd
commit
368eeb7da4
7 changed files with 185 additions and 5 deletions
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@ -36,6 +36,12 @@ config DPM_PM_FIRMWARE
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help
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The file name of the MediaTek DPM PM firmware.
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config MCUPM_FIRMWARE
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string
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default "mcupm.bin"
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help
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The file name of the MediaTek MCUPM firmware.
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config SPM_FIRMWARE
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string
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default "spm_firmware.bin"
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@ -34,7 +34,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
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ramstage-y += ../common/dpm.c ../common/dpm_v2.c
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ramstage-y += ../common/dramc_info.c
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ramstage-y += ../common/emi.c
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ramstage-y += ../common/mcu.c
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ramstage-y += ../common/mcu.c mcupm.c
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ramstage-y += ../common/memory.c
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ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
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ramstage-y += ../common/mt6315.c mt6315.c
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@ -58,6 +58,7 @@ MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189
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firmware-files := \
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$(CONFIG_DPM_DM_FIRMWARE) \
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$(CONFIG_DPM_PM_FIRMWARE) \
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$(CONFIG_MCUPM_FIRMWARE) \
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$(CONFIG_SPM_FIRMWARE)
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$(foreach fw, $(call strip_quotes,$(firmware-files)), \
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@ -4,10 +4,13 @@
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#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_ADDRESSMAP_H__
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enum {
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MCUCFG_BASE = 0x0C530000,
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DBGAO_BASE = 0x0D01A000,
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DEM_BASE = 0x0D0A0000,
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IO_PHYS = 0x10000000,
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GIC_BASE = 0x0C000000,
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MCUCFG_BASE = 0x0C530000,
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MCUPM_SRAM_BASE = 0x0C540000,
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MCUPM_CFG_BASE = 0x0C580000,
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DBGAO_BASE = 0x0D01A000,
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DEM_BASE = 0x0D0A0000,
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IO_PHYS = 0x10000000,
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};
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enum {
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67
src/soc/mediatek/mt8189/include/soc/mcupm_plat.h
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67
src/soc/mediatek/mt8189/include/soc/mcupm_plat.h
Normal file
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@ -0,0 +1,67 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_MCUPM_PLAT_H__
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#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_MCUPM_PLAT_H__
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#include <soc/addressmap.h>
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#define MCUPM_SW_RSTN MCUPM_CFG_BASE
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/*
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* SPM config:
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* Enable register access key, POWERON_CONFIG_EN = 0x0B160001
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*/
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#define DEVAPC_INFRA_SECU_AO_SEC_REPLACE_0 (DEVAPC_INFRA_SECU_AO_BASE + 0x0300)
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#define POLLING_ACK_RETRY_COUNTS 10
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#define POLLING_SRAM_RETRY_COUNTS 10
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/* CPUEB_PWR_CON (0x1C001000+0xEB4) */
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#define CPUEB_PWR_RST_B_LSB BIT(0)
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#define CPUEB_PWR_ISO_LSB BIT(1)
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#define CPUEB_PWR_ON_LSB BIT(2)
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#define CPUEB_PWR_ON_2ND_LSB BIT(3)
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#define CPUEB_PWR_CLK_DIS_LSB BIT(4)
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#define CPUEB_SRAM_CKISO_LSB BIT(5)
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#define CPUEB_SRAM_ISOINT_B_LSB BIT(6)
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#define CPUEB_SRAM_PDN_LSB BIT(8)
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#define CPUEB_SRAM_SLEEP_B_LSB BIT(9)
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#define SC_CPUEB_SRAM_PDN_ACK_LSB BIT(12)
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#define SC_CPUEB_SRAM_SLEEP_B_ACK_LSB BIT(13)
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#define SC_CPUEB_PWR_ACK_LSB BIT(30)
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#define SC_CPUEB_PWR_ACK_2ND_LSB BIT(31)
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#define MCUPM_SRAM_SIZE 0x30000 /* 192K Bytes */
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#define MCUPM_LOADER_SIZE 0x2300 /* CFG_MTCMOS_OFF_SUPPORT */
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#define MCUPM_TCM_SZ 0x30000 /* 192K */
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#define MCUPM_IMG_OFS 0x2300 /* CFG_MTCMOS_OFF_SUPPORT */
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#define MCUPM_RDMP_OFS 0x30000
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#define ABNORMALBOOT_REG_STATUS 0x0
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#define WARMBOOT_REG_STATUS 0x0
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#define MCUPM_RSTN_RESET 0x1F
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#define MCUPM_RSTN_RSTN_INIT 0x0
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#define MCUPM_CFGREG_SW_RSTN_SW_RSTN BIT(0)
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#define MCUPM_CFGREG_SW_RSTN_DMA_BUSY_MASK BIT(1)
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#define MCUPM_GPR_SIZE 0x64
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#define SRAM_GPR_SIZE 0x4 /* 4 Bytes */
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#define IPI_NUMBER 8
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#define IPI_MBOX_TOTAL IPI_NUMBER
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#define MBOX_SLOT_SIZE 0x4
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#define SRAM_SLOT_NUM 0x14 /* 0x14 = 20 slots = 20*4Bytes = 80 Bytes */
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#define PIN_S_NUM SRAM_SLOT_NUM
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#define PIN_R_NUM SRAM_SLOT_NUM
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#define MBOX_TABLE_NUM (PIN_S_NUM + PIN_R_NUM)
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#define GPR_BASE_ADDR_MCU(x) (MCUPM_SRAM_BASE + \
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MCUPM_SRAM_SIZE - \
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(IPI_MBOX_TOTAL * MBOX_TABLE_NUM * MBOX_SLOT_SIZE) - \
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MCUPM_GPR_SIZE + \
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((x) * SRAM_GPR_SIZE))
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#define MCUPM_INFO GPR_BASE_ADDR_MCU(0)
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#define ABNORMALBOOT_REG GPR_BASE_ADDR_MCU(1)
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#define WARMBOOT_REG GPR_BASE_ADDR_MCU(23)
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#endif
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@ -1027,6 +1027,7 @@ check_member(mtk_spm_regs, dp_tx_pwr_con, 0x0E80);
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check_member(mtk_spm_regs, scp_peri_pwr_con, 0x0E88);
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check_member(mtk_spm_regs, csi_rx_pwr_con, 0x0E9C);
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check_member(mtk_spm_regs, ssusb_pwr_con, 0x0EA8);
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check_member(mtk_spm_regs, cpueb_pwr_con, 0x0EB0);
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check_member(mtk_spm_regs, mfg0_pwr_con, 0x0EB4);
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check_member(mtk_spm_regs, mfg3_pwr_con, 0x0EC0);
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check_member(mtk_spm_regs, pwr_status, 0x0F40);
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100
src/soc/mediatek/mt8189/mcupm.c
Normal file
100
src/soc/mediatek/mt8189/mcupm.c
Normal file
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@ -0,0 +1,100 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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#include <console/console.h>
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#include <delay.h>
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#include <device/mmio.h>
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#include <soc/addressmap.h>
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#include <soc/mcu_common.h>
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#include <soc/mcupm.h>
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#include <soc/mcupm_plat.h>
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#include <soc/spm.h>
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#include <soc/symbols.h>
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static void reset_mcupm(struct mtk_mcu *mcu)
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{
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/* Clear abnormal boot register */
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write32p(ABNORMALBOOT_REG, ABNORMALBOOT_REG_STATUS);
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write32p(WARMBOOT_REG, WARMBOOT_REG_STATUS);
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write32(&mcupm_reg->sw_rstn, MCUPM_RSTN_RESET);
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}
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static struct mtk_mcu mcupm = {
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.firmware_name = CONFIG_MCUPM_FIRMWARE,
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.run_address = (void *)MCUPM_SRAM_BASE,
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.reset = reset_mcupm,
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};
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void mcupm_init(void)
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{
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mcupm.load_buffer = _dram_dma;
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mcupm.buffer_size = REGION_SIZE(dram_dma);
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/* Set CPUEB as secure master */
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setbits32(&mtk_spm->poweron_config_set, BIT(15));
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/* Unlock SPM POWERON_CONFIG_EN */
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setbits32(&mtk_spm->poweron_config_set, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
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/* Reinit CPUEB_PWR_CON */
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/* (1) CPUEB MTCMOS */
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setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_ON_LSB);
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setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_ON_2ND_LSB);
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u32 pwr_con_mask = SC_CPUEB_PWR_ACK_LSB | SC_CPUEB_PWR_ACK_2ND_LSB;
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if (!retry(POLLING_ACK_RETRY_COUNTS,
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((read32(&mtk_spm->cpueb_pwr_con) & pwr_con_mask) == pwr_con_mask),
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udelay(1))) {
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printk(BIOS_ERR, "%s Polling ACK timeout, %#x\n", __func__,
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read32(&mtk_spm->cpueb_pwr_con));
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return;
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}
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clrbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_CLK_DIS_LSB);
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clrbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_ISO_LSB);
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setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_PWR_RST_B_LSB);
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/* (2) SRAM leave DORMANT mode */
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setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_SRAM_SLEEP_B_LSB);
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if (!retry(POLLING_ACK_RETRY_COUNTS,
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((read32(&mtk_spm->cpueb_pwr_con) & SC_CPUEB_SRAM_SLEEP_B_ACK_LSB) != 0),
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udelay(1))) {
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printk(BIOS_ERR, "%s Polling SRAM Sleep B ACK timeout, %#x\n", __func__,
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read32(&mtk_spm->cpueb_pwr_con));
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return;
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}
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udelay(1);
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setbits32(&mtk_spm->cpueb_pwr_con, CPUEB_SRAM_ISOINT_B_LSB);
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clrbits32(&mtk_spm->cpueb_pwr_con, CPUEB_SRAM_CKISO_LSB);
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/* Power on MCUPM sram */
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clrbits32(&mtk_spm->cpueb_pwr_con, CPUEB_SRAM_PDN_LSB);
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pwr_con_mask = SC_CPUEB_SRAM_PDN_ACK_LSB;
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if (!retry(POLLING_SRAM_RETRY_COUNTS,
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(read32(&mtk_spm->cpueb_pwr_con) & pwr_con_mask) != pwr_con_mask,
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udelay(1))) {
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printk(BIOS_ERR, "%s Polling SRAM Power on timeout, %#x\n", __func__,
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read32(&mtk_spm->cpueb_pwr_con));
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return;
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}
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printk(BIOS_INFO, "%s Power on MCUPM SRAM success\n", __func__);
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write32(&mcupm_reg->sw_rstn, MCUPM_RSTN_RSTN_INIT);
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if (mtk_init_mcu(&mcupm))
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die("%s() mtk_init_mcu failed\n", __func__);
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setbits32p(MCUPM_SW_RSTN,
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MCUPM_CFGREG_SW_RSTN_SW_RSTN | MCUPM_CFGREG_SW_RSTN_DMA_BUSY_MASK);
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printk(BIOS_DEBUG, "mcupm: MCUPM_SRAM_GPR0: %#x, %#x\n",
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MCUPM_INFO, read32p(MCUPM_INFO));
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printk(BIOS_DEBUG, "mcupm: MCUPM_SRAM_GPR1: %#x, %#x\n",
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ABNORMALBOOT_REG, read32p(ABNORMALBOOT_REG));
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printk(BIOS_DEBUG, "mcupm: MCUPM_SRAM_GPR23: %#x, %#x\n",
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WARMBOOT_REG, read32p(WARMBOOT_REG));
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printk(BIOS_DEBUG, "mcupm: MCUPM_SW_RSTN: %#x, %#x\n",
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MCUPM_SW_RSTN, read32p(MCUPM_SW_RSTN));
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printk(BIOS_DEBUG, "mcupm: MCUPM_SRAM_BASE: %#x, %#x\n",
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MCUPM_SRAM_BASE, read32p(MCUPM_SRAM_BASE));
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printk(BIOS_DEBUG, "%s MCUPM part. load & reset finished\n", __func__);
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}
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@ -4,6 +4,7 @@
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#include <device/device.h>
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#include <soc/dramc_info.h>
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#include <soc/emi.h>
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#include <soc/mcupm.h>
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#include <symbols.h>
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void bootmem_platform_add_ranges(void)
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@ -18,6 +19,7 @@ static void soc_read_resources(struct device *dev)
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static void soc_init(struct device *dev)
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{
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mcupm_init();
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}
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static struct device_operations soc_ops = {
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