soc/mediatek/common: Refactor auxadc driver to support new platform

The method for reading AUXDAC on mt8189 differs from previous methods.
To enhance code modularity and maintain compatibility, the differing
parts are moved to auxad_v1.h  to supports legacy platforms.

BUG=b:379008996
BRANCH=none
TEST=emerge-geralt coreboot -j

Change-Id: Ib4bf0f593cab0480b7c78df7916f721f2e0833c7
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/common/auxadc.c

@@ -10,10 +10,6 @@
 
 static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE;
 
-#define ADC_GE_A_SHIFT		10
-#define ADC_GE_A_MASK		(0x3ff << ADC_GE_A_SHIFT)
-#define ADC_OE_A_SHIFT		0
-#define ADC_OE_A_MASK		(0x3ff << ADC_OE_A_SHIFT)
 #define ADC_CALI_EN_A_SHIFT	20
 #define ADC_CALI_EN_A_MASK	(0x1 << ADC_CALI_EN_A_SHIFT)
 
@@ -38,7 +34,7 @@ static void mt_auxadc_update_cali(void)
 
 static uint32_t auxadc_get_rawdata(int channel)
 {
-	setbits32(&mtk_infracfg->module_sw_cg_1_clr, 1 << 10);
+	setbits32(&AUXADC_SWCG_CLR_REG, BIT(AUXADC_SWCG_EN_BIT));
 	assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1)));
 
 	clrbits32(&mtk_auxadc->con1, 1 << channel);
@@ -50,7 +46,7 @@ static uint32_t auxadc_get_rawdata(int channel)
 
 	uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF;
 
-	setbits32(&mtk_infracfg->module_sw_cg_1_set, 1 << 10);
+	setbits32(&AUXADC_SWCG_SET_REG, BIT(AUXADC_SWCG_EN_BIT));
 
 	return value;
 }

src/soc/mediatek/common/include/soc/auxadc_v1.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_COMMON_INCLUDE_SOC_AUXADC_V1_H__
+#define __SOC_MEDIATEK_COMMON_INCLUDE_SOC_AUXADC_V1_H__
+
+#define ADC_GE_A_SHIFT		10
+#define ADC_GE_A_MASK		(0x3ff << ADC_GE_A_SHIFT)
+#define ADC_OE_A_SHIFT		0
+#define ADC_OE_A_MASK		(0x3ff << ADC_OE_A_SHIFT)
+
+#define AUXADC_SWCG_CLR_REG	(mtk_infracfg->module_sw_cg_1_clr)
+#define AUXADC_SWCG_SET_REG	(mtk_infracfg->module_sw_cg_1_set)
+#define AUXADC_SWCG_EN_BIT	10
+
+#endif

src/soc/mediatek/mt8183/include/soc/auxadc.h

@@ -4,6 +4,7 @@
 #define _MTK_ADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>
 

src/soc/mediatek/mt8186/include/soc/auxadc.h

@@ -9,6 +9,7 @@
 #define SOC_MEDIATEK_MT8186_AUXADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>
 

src/soc/mediatek/mt8188/include/soc/auxadc.h

@@ -9,6 +9,7 @@
 #define SOC_MEDIATEK_MT8188_AUXADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>
 

src/soc/mediatek/mt8192/include/soc/auxadc.h

@@ -4,6 +4,7 @@
 #define _MTK_ADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>
 

src/soc/mediatek/mt8195/include/soc/auxadc.h

@@ -4,6 +4,7 @@
 #define SOC_MEDIATEK_MT8195_AUXADC_H
 
 #include <soc/auxadc_common.h>
+#include <soc/auxadc_v1.h>
 #include <soc/infracfg.h>
 #include <stdint.h>