soc/qualcomm/x1p42100: Enable basic PCIe support

This commit introduces initial support for PCI Express on the
Qualcomm x1p42100 SoC.

Key changes include:
- Selecting `CONFIG_PCI` in Kconfig to enable general PCI subsystem
  support for this SoC.
- Selecting `CONFIG_NO_ECAM_MMCONF_SUPPORT`, indicating that this
  platform will not use the standard MMCONFIG ECAM for PCI
  configuration space access. An alternative mechanism will be required.
- Adding `../common/pcie_common.c` to the ramstage build if `CONFIG_PCI`
  is enabled, incorporating common PCIe helper functions.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: I53e8bb3ce8551e8fa8c4b1cd39d89e12226c32f1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87858
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/qualcomm/x1p42100/Kconfig

@@ -21,6 +21,8 @@ config SOC_QUALCOMM_X1P42100
 	select HAVE_UART_SPECIAL
 	select MAINBOARD_FORCE_NATIVE_VGA_INIT
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select PCI
+	select NO_ECAM_MMCONF_SUPPORT
 	select SDHCI_CONTROLLER
 	select SOC_QUALCOMM_COMMON
 

src/soc/qualcomm/x1p42100/Makefile.mk

@@ -38,6 +38,7 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
 ramstage-y += soc.c
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
+ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
 ramstage-y += cpucp_load_reset.c
 
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