Matt DeVillier 9f8e5ab661 soc/intel/cmn/block/aspm: Use separate option variable for CPU RP ... Since the default ASPM UPD value (and valid values) differ between CPU and PCH-attached root ports, add a new option variable for CPU-attached RPs so that they are not inadvertently set to an invalid value, leading ASPM to be disabled on those RPs. Change-Id: I66ec77a3774a96cfe11f5827f5ba711ec826b236 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>		2025-06-07 18:45:28 +00:00
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amd	soc/amd/glinda: Don't let OS put debug UART into D3	2025-06-04 18:00:06 +00:00
cavium	soc/cavium: Fix non matching types	2024-08-30 07:34:47 +00:00
example/min86	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
ibm/power9	3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER	2024-09-06 13:55:50 +00:00
intel	soc/intel/cmn/block/aspm: Use separate option variable for CPU RP	2025-06-07 18:45:28 +00:00
mediatek	soc/mediatek/mt8189: Enable MUXes for improved peripheral stability	2025-06-07 09:50:11 +00:00
nvidia	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
qualcomm	soc/qualcomm/x1p42100: Enable basic PCIe support	2025-05-30 04:21:29 +00:00
rockchip	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive	tree: Remove unused <assert.h>	2024-11-19 00:40:04 +00:00
ti	soc/ti/am335x: Remove superfluous formats	2024-08-02 14:45:13 +00:00
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00