This patch applies commit 0e7cf3d81d ("soc/intel/alderlake: Fix DDR5
channel mapping") to Meteor Lake.
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Meteor
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.
To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.
Change-Id: I00cd1fba855a50422a68fa662df4ca8ed2c6458d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88636
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5.
Now that DDR5 SPD EEPROM reading has been fixed in commit e9cb352706
("soc/common/smbus: Support reading SPD5 hubs for DDR5"), remove the
now unneeded workaround for DDR5 and use coreboot's SPD read as we
do for all other module types.
Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75284
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Introduce the disable_progress_bar setting in configuration to allow
disabling the memory training progress bar during firmware
initialization.
BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar
is disabled.
Change-Id: I35e8191df27c0eda634724580514e980bd620136
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).
Ref: DDR5 SDRAM spec, JESD79-5C.01
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52731
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These will be used in subsequent patches which optimize the reading of
SPDs based on the supported memory type(s).
Change-Id: I8b0d4f37b4b992c42bede25d678cb9afc9db3dd6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88521
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The magic number '1' for VgaInitControl is replaced with the
VGA_INIT_CONTROL_ENABLE macro for improved readability and
maintainability.
This makes the code's intent clearer and aligns with best practices
for using named constants.
The VGA_INIT_CONTROL_ENABLE macro is defined in ux.h along with a
comment to describe its purpose.
TEST=Able to see eSOL while booting google/fatcat.
Change-Id: I27a91030c0aaa52e099869c5870da670d3e28628
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit assigns pci_dev_request_bus_master to the .final operation
for both the DSP and HDA device operations to ensure that the bus
master is enabled.
This change ensures correct PCI configuration for DSP and HDA devices,
preventing potential issues with direct memory access operations.
BUG=b:427091370
TEST=Able to build and boot google/fatcat.
w/o this patch
```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x02
```
w/ this patch:
```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x06
```
Change-Id: Id2480dba08ea8ee7a9219327b8a31f8f9f65410c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
After crash data extraction, the records are cleared and reinitialized
to their default values. This is done using watcher interface instead
of BIOS mailbox commands because of low latency and efficiency.
Ref: LNL FAS 733648
BUG= b:None
TEST= iotools mmio_dump 0x9c199d40 0x10 - PMC
0x000000009c199d40: 0xdeadbeef 0xdeadbeef 0xdeadbeef 0xdeadbeef
iotools mmio_dump 0x9c1d0058 0x10 - CPU
0x000000009c1d0058: 0xcafecafe 0xcafecafe 0xcafecafe 0xcafecafe
Initial 8 bytes of header are zeroes - indicating that both header
and crashlog data buffer are cleared
Change-Id: I8a36e091f61833067caf9e9f94ba79149e699d68
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
FSP-T will help to cache bios region along with MTRR programming
by setting CodeRegionBase/CodeRegionLength, thus there is no need
for xeon_sp platforms to do it.
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/archercity CRB
Check MTRR usage and below duplicated MTRR item get removed:
[DEBUG] 0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP
[DEBUG] 0x000fffffff000800: PHYMASK1: Length = 0x0000000001000000, Valid
Change-Id: Ia414a35c663f3aa1b02d944475a96e11d07a4f00
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Drop the custom function to retrieve the value of multiple GPIOs
at once as integer value and use the generic function prototype
defined in include/gpio.h instead.
Therefore:
* select GENERIC_GPIO_LIB
* Stub gpio_input(). Existing code assumes the pin is input.
* Drop get_gpios() implementation
* Include new header file gpio.h
* Migrate pins from type int to gpio_t
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I2296ff72231b569c618295b36b95a89ffebb3a6e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88503
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to use the common gpio.h header file typedef gpio_t in
soc/gpio.h for Intel common code, Intel lynxpoint and Intel broadwell.
Change-Id: I2049a2cfd75c60d00bdd564b294808760b6aff7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename config options 'USE_DDRx' to 'DRAM_SUPPORT_DDRx' to make them
less clunky, and in preparation to expand their use inside SoC code.
Change-Id: Ie6edd730c5cbad679a90fcf7989a942d9b2dd3d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit introduces support for asynchronous coreboot File
System (CBFS) file loading from SPINOR, specifically targeting the
fsps.bin file, in the Intel Panther Lake (PTL) System on a Chip (SoC)
platform. The primary motivation for this change is to improve boot time
performance by utilizing SPI Direct Memory Access (DMA) to preload files
while the Central Processing Unit (CPU) continues executing other tasks.
This feature uses cooperative multithreading. Because the scheduling is
cooperative, the boot process stays mostly predictable, which minimizes
debugging difficulties while still enhancing boot performance.
The preload operations are strategically modified according to the
chipset lockdown settings. This guarantees that payload preloading is
finalized prior to SPI DMA locking when the chipset lockdown is managed
by FSP or otherwise maximizes the pre-loading feature.
Note: As there is no UPD to control the Fast DMI DMA interface lockdown,
a special FSP binary, built without the Fast SPI DMA driver
(PcdSpiDmaEnable), is required when chipset lockdown setting is set to
CHIPSET_LOCKDOWN_COREBOOT.
TEST=On a Fatcat device, with CHIPSET_LOCKDOWN_COREBOOT, the boot time
has improved by around 17-18 ms.
Change-Id: I4106058d382b99eac5f988c134cc02f024f7d473
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88300
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements a token-based queuing system to reduce delays
between consecutive DMA operations. The queuing mechanism aims to
improve overall throughput.
A Kconfig option FAST_SPI_DMA_QUEUE_SIZE defines the maximum number of
concurrent DMA transfers that can be queued and processed.
When DMA transfers are queued, a new thread is initiated to run
fast_spi_dma_main_thread(). This function consistently monitors for
available transfer tokens and performs DMA operations when tokens are in
the DMA_REQUESTED state. If there are no tokens in the desired state,
the thread_running flag is set to false, and the thread terminates
smoothly.
While it provides a barely perceptible boot time improvement with the
Panther Lake configuration, it makes the boot flow more consistent and
predictable.
TEST=On a Fatcat device with CBFS_PRELOAD enabled and set up, we observe
consecutive logs as follows, proving a new DMA transfer is issued
as soon as the previous one's completion is detected.
[DEBUG] Fast-SPI: transfer completed in 2574 us
[DEBUG] Fast-SPI: Reading 240 blocks via DMA
Change-Id: Ic5249362041cfa028885874b43893e1d7942ed94
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
In PTL Crashlog Watcher interface is used instead of Mailbox since it
is based on the Intel Platform Monitoring Technology (PMT) standard.
The Watcher interface provides a more flexible and efficient way to
control and monitor crashlog collection. Hence the functionalities like
rearm and clear are implemented using watcher interface instead of BIOS
mailbox to PUNIT.
Change-Id: I24c5c9753a577b255a7129d20ab83f93001a0485
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88500
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
After the BIOS reads and processes the crashLog record, it sets the
CONSUMED_BIOS bit to indicate that the reading and storing of crashlog
record is complete. This is read only bit. When this bit is set ,
crashlog discovery and data collection are skipped. This bit helps in
preventing the same crashLog from being extracted multiple times after
a reset.
BUG= b:None
TEST= The header value during warm boot after crash
cpu_cl_disc_tab.header.data dw0=88420003, dw1=0x0
Change-Id: I4b9e6900218f28b6beb71b7667bc1c57f0134a84
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88499
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
This patch refactors the BMP rendering logic, moving it from
drivers/intel/fsp2_0 to src/lib. This centralizes the code
responsible for rendering BMP images to the framebuffer.
Key changes:
- Move BMP rendering functions (e.g., calculate_logo_coordinates,
copy_logo_to_framebuffer) and their dependencies to
src/lib/render_bmp.c and src/lib/render_bmp.h.
- Decouple BMP definitions from UEFI headers by introducing new
coreboot-specific structures for BMP images and BLT pixels.
- Consolidate bootsplash-related declarations into bootsplash.h,
including new `fw_splash_vertical_alignment`,
`fw_splash_horizontal_alignment`, and `struct logo_config`.
- Update `soc_load_logo_by_coreboot` to use the new common
`load_and_render_logo_to_framebuffer` function and `struct
logo_config` for rendering.
- Relocate `release_logo` to `src/lib/render_bmp.c` for better
module structure.
- Update `src/lib/Makefile.mk` to include the new render_bmp.c.
This refactoring improves code organization and reusability, making
BMP rendering accessible without tight coupling to Intel-specific
driver code.
BUG=b:427387842
TEST=Verify firmware splash screen on google/fatcat.
Change-Id: I0e20ea7e44b4b3ccdb2d4aa9b6aa10ed3447ccfc
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88361
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a DMA lock mechanism to secure the Fast SPI DMA operations
during the payload boot phase. A new `fast_spi_dma_lock` function is
added to lock the DMA control register when the system enters the
payload boot state. This ensures that DMA operations are appropriately
secured, preventing any unintended data transfers post-boot.
TEST=On a Fatcat device with an FSP not locking down Fast SPI DMA,
coreboot logs show "Fast-SPI: DMA has been locked." and
/sys/devices/pci0000:00/0000:00:1f.5/config shows that bit 15 of
register FAST_SPI_DMA_CONTROL (0xbc) has been is set.
Change-Id: Ie4abbcfc798480319a32b0049e3559d623ef78ef
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88488
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use microcode updates from intel-microcode submodule by default.
Downstream users can still decide to use their own files.
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB
Change-Id: I5a37423426b19dc9ec76984df5ad9c6d2a28f83b
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
IBL shall use PMC device to program ABASE instead of PCR.
TESTED=Build and boot on intel/avenuecity CRB with below log:
[INFO ] soc_config_acpibase : pmbase = 501
Change-Id: I3497c287a5370deed02b269405bc45d5d41e7f33
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88144
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get information about the current Boot Guard implementation, such as
whether it's enabled, the profile and if Measured Boot or Verified
Boot are required.
Then, measure the three individual components of the BIOS.
Tested on the StarLite Mk III where all three components were measured
successfully:
[DEBUG] Boot Guard 2.0: Verified Boot: Enforced
[DEBUG] Boot Guard 2.0: Measured Boot: Enforced
[DEBUG] TXE Hash:
[DEBUG] 0xfef08f5e: ...
[DEBUG] 0xfef08f6e: ...
[DEBUG] IBBL Hash:
[DEBUG] 0xfef08f7e: ...
[DEBUG] 0xfef08f8e: ...
[DEBUG] IBB Pointer: Present
...
[DEBUG] IBB Hash:
[DEBUG] 0xfef08f9e: ...
[DEBUG] 0xfef08fae: ...
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia962ae40b411671e82540b19f3b8680529783711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 060df17f1d ("soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM")
set the default to Firmware Connection Manager, as linux commit
c6da62a219d028de10f2e22e93a34c7ee2b88d03 did not work correctly with
Software Connection Manager.
This issue was fixed with linux commit
719e1f561afbe020ed175825a9bd25ed62ed1697, so now that Software
Connection Manager works, default to it for normal builds as well as
ChromeOS ones.
Change-Id: I4393fc4992d602b7214929592f542270002d84ec
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Details:
- First set files to compile google/ocelot mainboard w.r.t. WCL FSP
3266_02.
- Change file path for the FSP_HEADER_PATH for WildacatLake.
BUG=b:431683053
TEST=Build Ocelot without any errors.
Change-Id: Iec31b0055bc145d795adef6723511ac07f83406b
Signed-off-by: alokagar <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88433
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Measured Boot that is specific to Apollolake, and is used
for measuring the IBBL, IBB and TXE. The IBB is measured only if it
exists, and only after it has been loaded into the CSE.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I61ce4a34875d6d3357d4088167cdd887bafdff23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65272
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Copy the IBB into CAR via the CSEs RBP to ensure it has not been
modified.
Test on the StarLite Mk III and Mk IV:
Without VBOOT:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: IBB Size : 88
With VBOOT:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: IBB Size : 102
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0d4e26834cef4c876e37e414b424a031c11111ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a loader that will load the IBB into the CSE via the Ring Protocol
Buffer.
All registers were taken from Intel document number #336561.
Change-Id: Ia41e3909f8099d2ea864166e9ea03e10e40a1b68
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65270
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot's method of creating IFWI is to modify an existing IFWI
images by deleting the IBB, replacing the IBBL with the bootblock
and everything else is put in the OBB.
This poses a problem when using Intel's FIT or technologies such
as Boot Guard. The main problem is that the IBB is never verified by
the CSE or copied from SRAM to CAR, so the CSE cannot complete BUP
and stays in recovery mode. The vast majority of the stages in
Apollolake's Secure Boot flow is not met using this method (Intel
document number 597827 summarizes these steps).
This patch series is based on the principles of a patch from Brenton
Dong (CB:17064) creates an IBBL, IBB and OBB binaries with the
correct functions to complete the Secure Boot flow. This is to copy
the IBB from SRAM using the CSE's Ring Buffer Protocol.
These binaries can then be used by FIT or coreboot's existing
method of hacking IFWI together (IFWI_STITCH) via IFWITOOL. If it is
the latter and Boot Guard is enabled, the hashes for IFWI and "ibb+obb"
must be recreated.
Whilst this option doesn't form a complete image, the components it
builds will work as Intel intended them to once stitched correctly into
an IFWI image.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This configures FSP UPDs for PCH PM minimum assertion widths and
reset power cycle duration per mainboard variants configuration.
This also checks the reset power cycle duration is not be smaller
than SLP_S3, SLP_S4 and SLP_A Minimum Assertion Width.
PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
The Reset Power Cycle Duration starts at 20ms and increases by 20ms
for each step, beginning from 0x0 to 0xFF. Each subsequent increment
corresponds to an additional 20 milliseconds in duration.
Reference:
Panther Lake External Design Specification (EDS) Volume 2 (#813032)
BUG=None
TEST=Build a fatcat coreboot and boot to OS without an issue.
Change-Id: I7234c7539c1e7eb5e2b8c04ccff6c62c853d6807
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88443
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch introduces a new configuration option
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` that allows users to
specify if their mainboard is using Panther Lake pre-production silicon
aka Engineering Silicon (ES) with pre-production signed ME Firmwares.
The default value is set to 'n', ensuring it is disabled unless
explicitly chosen.
BUG=b:424355826
TEST=No change in the functionality, just added new configs.
Change-Id: I8ad83b07f057a227b62e33b6c6c0f46c3952be6b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88218
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces Direct Memory Access (DMA) support for the Intel
Fast SPI block, enhancing data transfer capabilities from SPI flash
memory. The primary motivation for this addition is to improve
performance in multitasking environments by offloading read operations
to DMA, thus freeing up CPU resources for other tasks. The traditional
memory-mapped SPI flash read operations can be CPU-intensive and slow in
scenarios where large data volumes are transferred.
This feature is gated by a FAST_SPI_DMA configuration option. The DMA
operations are integrated with existing SPI flash read functionalities,
ensuring fallback to memory-mapped operations if DMA is unsupported or
fails. The DMA code implementation uses mutex-based synchronization to
ensure thread-safe DMA transactions.
The boot_device_ro() function has been modified to check for DMA support
and installs custom DMA operations when available.
We conducted measurements on a 200 KB data transfer and noticed a 1.8%
improvement with DMA compared to memcpy on memory-mapped SPINOR, with
DMA taking 10.8 ms and memcpy taking 11 ms.
Change-Id: I4b4ca9ff08e436ca627afa6b0d9bb00f3c450a5e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88277
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Boot Profile for use with the IFWI Boot Flow. The selected profile
should be equal to or higher than the one configured in IFWI.
No Profile
Since its inception, coreboot has ignored the Boot Flow designed by
Intel; this only uses an IBB and OBB. Neither are measured or verified
and mapped without assistance.
Legacy
Profile 0 is for platforms that do not wish to enable Boot Guard boot
block verification or measurement enforcement.
Verified
Profile 1 is strict Verification enforcement. It prevents unverified
BIOS components from running.
Verified and Measured
Boot Guard Profile 2 is strict Verification and Measurement
enforcement; this prevents unverified BIOS components from running.
Upon manufacturing completion, this value is burned into an FPF
and is permanent. This setting is only configurable when OEM signing
is enabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I83d2fd134e1a893766f625fe2e2ddd81d48f9f8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66103
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There can be cases where it is needed to provide the SPD data in a
different way than an EEPROM or CBFS file. This patch adds a third
method where the SPD data can be provided in a memory buffer for
memory-down configurations. Where this memory buffer comes from
and how SPD data is filled in is up to the mainboard code.
To use this new method set 'spd_data.in_mem' to 'true' and provide a
pointer to the SPD data in memory via 'spd_data.ptr' where
'spd_data.len' holds the length of the SPD data in that buffer.
This feature is useful for Siemens mainboards where the SPD data is part
of a larger configuration block called 'HWInfo block'. Though this block
itself do reside in CBFS, the SPD data cannot simply be indexed into
(like with the cbfs_index). Instead, the hwinfo-lib is used to get
dedicated fields from that block, this includes the SPD data, too. With
this patch the SPD data can be retrieved from HWInfo block and passed as
a buffer to the memory initialization code.
Change-Id: I2bd4970967cfe81bba96d8e2b2fd3a0bb85430c4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88258
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the platform reporting logic to recognize the
Wildcat Lake SoC CPU ID.
Key changes:
- Add CPUID_WILDCATLAKE_A0 to the list of recognized CPU IDs in
the platform reporting module.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I8c9e81446a12ee0a6e18f1ba3f36166652a05f5e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88271
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces a new MCH device ID to support the Wildcat
Lake SoC. It updates the PCI device ID list and platform reporting
logic to accommodate this new ID.
Key changes:
- Add PCI_DID_INTEL_WCL_ID_3 (0xfd02) to the list of recognized
device IDs.
- Update system agent operations to include the new MCH ID.
- Enhance platform reporting to recognize the new MCH ID.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I464fb147f0d3df214ca64b1321eebab08505d7bc
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88248
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Add parameters and default setting of FSP
BUG=b:407645233
TEST= IOMT verification confirmed, that USB settings can be updated through FSP parameters.
Change-Id: Idbd9ee795b74f43921472ef42a95b2be23af6f5d
Signed-off-by: Doris Hsu <doris.hsu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This reverts commit 2e495b09d5.
Reason for revert: mmio_tseg is reserved twice in
mc_add_dram_resources, where the duplication is introduced by
commit 43b0ed7089 ("soc/intel/xeon_sp: Improve final MTRR solution")
Change-Id: I0f1bf757d8d1fc449e4efc0ec171c6f982f79e9e
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Introduces logo_bottom_margin to soc_intel_common_config to allow
adjusting the vertical (or horizontal, based on orientation) offset of
the footer logo from the screen edge. This provides flexibility for
OEM branding placement.
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat.
Change-Id: Ie3942d9eee07091286118ac488d1cc85ecc96c4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Currently, the overcurrent pin enum is only defined up to OC5. However,
PCH-H chips support up to OC7 according to the 100 and 200 Series PCH
datasheets [1][2].
[1] Intel document 332690
[2] Intel document 335192
Change-Id: Ie35612eeaed2196caccc514429c7d80f84cf09a8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88159
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This partially reverts commit 32ebaef73c
("mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE")
as google/brox board has moved away from the PAD_CFG_GPI_INT_SWAPPED
usage. The revert simply removes the PAD_CFG_GPI_INT_SWAPPED solution,
which is not used anywhere anymore.
PAD_CFG0_ROUTE_SWAPPED bit can not be found in any PCH datasheet nor
EDS. Furthermore, the definition conflicts with PAD_CFG0_NAFVWE_ENABLE
bit, which, on the contrary, is defined in the datasheets and PCH EDS.
The conflict results in boards printing:
"GPIO XX doesn't support APIC routing," (where XX is pad number)
for each pad having the NAFVWE bit set.
Currently, none of the boards use PAD_CFG0_ROUTE_SWAPPED bit, and due
to the bit field conflict I assume it was mistakenly added.
Change-Id: I71299c9729f294cfafaec02222ef01e96b575740
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87485
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit addresses an issue within the DMAR (DMA Remapping) table
configuration for Intel Panther Lake (PTL) SoC. Specifically, it
introduces telemetry support to the DRHC structure. In addition, the
unnecessary Dynamic Platform and Thermal Framework (DPTF) entry is
removed from the SATC structure, aligning with the BIOS Requirements.
For detailed specifications, refer to the 812562 PTL Firmware
Architecture Specification (FAS).
BUG=b:423943431
TEST=Boot Fatcat board to ALOS. Disassemble the DMAR table using 2023+
version of iasl and check the DMAR for the telemetry entry in the DRHC
structure. There should not be a DPTF entry in the SATC structure.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I289f2520e4449a6aa33f53040b6c8f66faa4f2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88136
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A need arose to perform power and performance analysis on various SoC
SKUs with Fast VMode enabled, which the current chipset data structure
does not allow.
This commit refactors the configuration of Fast VMode I_TRIP thresholds
for Voltage Regulator (VR) domains across different power limit
configurations in Pantherlake SoCs. Previously, the I_TRIP threshold
values were statically set for each VR domain, but now they are defined
within a two-dimensional array that considers various power limit
scenarios.
This commit adds the I_TRIP values for different Power Limit SKUs
currently operated on Fatcat devices.
As part of this commit, the following two changes are being undone
because the previous code structure is now incompatible and lacks
purpose:
- commit 4b765fdd98 ("mb/google/fatcat: Disable EnableFastVmode on
Panther Lake H SoC")
- commit 5d7e2b4c0c ("mb/google/fatcat: Disable VR settings on Panther
Lake H SoC")
Change-Id: Iff21a9b0b230e08b99e032400cbe0021b8a4af43
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit adds the relevant IDs to support new Panther Lake (PTL)
System on Chips (SoCs). The CPU profiles are aligned with the matching
definition from Panther Lake Firmware Support Package (FSP) revision
3144.01.
TEST=A Fatcat device with CPUID 0xc06c1 and MCH_ID 0xb003 booted with
the relevant information printed in corebot logs.
[DEBUG] CPU: ID c06c1, Pantherlake B0, ucode: 00000105
[DEBUG] MCH: device id b003 (rev 06) is Pantherlake U
[DEBUG] PCH: device id e401 (rev 01) is Pantherlake SOC-H SuperSKU
[DEBUG] IGD: device id b090 (rev 00) is Pantherlake-U GT2
Change-Id: I66efe51a94edfffc2546817d06a63a9c4b51aa81
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88130
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit introduces the configuration and enabling of Thermal Design
Current (TDC) settings for various Panther Lake (PTL) SKUs. TDC values
are essential for managing thermal constraints, specifying the maximum
allowable current for specific Voltage Regulator (VR) domains under
given power limit scenarios. This enhancement provides tailored power
management for different SKUs, extracted from the Power Map Document
(#813278) which the Firmware Support Package (FSP) is not aligned with.
It introduces a new enum `soc_intel_pantherlake_sku` to represent
various SKUs as the current `soc_intel_pantherlake_power_limits` does
not meet the need for TDC settings. `cpuid_to_ptl` is updated to include
SKU mapping.
The VR romstage FSP params function implements logic to read SKU
information based on PCI device ID and CPU TDP, ensuring accurate
configuration.
TEST=FSP logs confirm TDC enablement at the specified values on a Fatcat
device operating an H12Xe Panther Lake SoC.
Change-Id: I889d5f08b0c75b950e5a30d25d6a370cccd295aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit makes power limit helper functions accessible during
romstage by updating the Makefile to include `power_limit.c` for both
ramstage and romstage.
It also modifies a preprocessor directive to ensure
`variant_update_cpu_power_limits()` is not compiled in romstage as it is
only intended for late-in-the-boot usage and will not compile properly
in romstage.
This change enables power management configuration identification early
in the boot process, allowing for better control over power settings at
this stage.
TEST=Successfully compile the Fatcat board target.
Change-Id: Ibf4d85c71dd8963063ca014d151438b68ea918db
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous default value of 10 milliseconds is being updated to 50
milliseconds to comply with the latest guidelines (Panther Lake FSP
release 3144.01 CnviWifi.asl file).
TEST=Invoke the following set of acpidbg commands to verify that the
_RST method still reaches state 2.
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x2
Change-Id: I2b0236c17117d368c1ee98e56c4c1b6525d63e27
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
