erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/xeon_sp/gnr: Implement get_mmio_high_base_size

Browse source 
Report above 4G MMIO base and size to coreboot so that coreboot
could correctly set MTRR coverage for the whole region instead
of only covering PCI driver used parts, where much fragmentation
was introduced.

TESTED=Build and boot on intel/avenuecity CRB, check MTRR usage:
[DEBUG]  0x0000000080000000: PHYBASE0: Address = 0x0000000080000000, UC
[DEBUG]  0x000fffff80000800: PHYMASK0: Length  = 0x0000000080000000, Valid
[DEBUG]  0x00001e0000000000: PHYBASE1: Address = 0x00001e0000000000, UC
[DEBUG]  0x000fff0000000800: PHYMASK1: Length  = 0x0000010000000000, Valid
[DEBUG]  0x00001f0000000000: PHYBASE2: Address = 0x00001f0000000000, UC
[DEBUG]  0x000fffc000000800: PHYMASK2: Length  = 0x0000004000000000, Valid
[DEBUG]  0x0000000000000000: PHYBASE3
[DEBUG]  0x0000000000000000: PHYMASK3: Disabled

Change-Id: I61a7e96b3e7566d6a2c14951e7eb4f0be98c13e5
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88279
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jincheng Li 2025-06-23 11:10:14 +08:00 • committed by Matt DeVillier
commit ced4c09359
1 changed files with 5 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/soc/intel/xeon_sp/gnr/soc_util.c
View file

@ -165,5 +165,9 @@ bool is_memtype_processor_attached(uint16_t mem_type)
bool get_mmio_high_base_size(resource_t *base, resource_t *size)
{
return false;
const IIO_UDS *hob = get_iio_uds();
*base = hob->PlatformData.SystemMmio64Base;
*size = hob->PlatformData.SystemMmio64Limit - (*base) + 1;
return true;
}