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soc/intel/apollolake: Load the IBB into CAR

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Copy the IBB into CAR via the CSEs RBP to ensure it has not been
modified.

Test on the StarLite Mk III and Mk IV:
Without VBOOT:
    [DEBUG]  CSE: IBB Verification Result: PASS
    [DEBUG]  CSE: IBB Verification Done  : YES
    [DEBUG]  CSE: IBB Size               : 88

With VBOOT:
    [DEBUG]  CSE: IBB Verification Result: PASS
    [DEBUG]  CSE: IBB Verification Done  : YES
    [DEBUG]  CSE: IBB Size               : 102

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0d4e26834cef4c876e37e414b424a031c11111ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2022-06-30 21:22:59 +01:00 • committed by Matt DeVillier
commit 289cff3423
1 changed files with 7 additions and 1 deletions
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8
src/soc/intel/apollolake/bootblock/bootblock.c
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@ -15,8 +15,9 @@
#include <intelblocks/pmclib.h>
#include <intelblocks/tco.h>
#include <intelblocks/uart.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/loader.h>
#include <soc/gpio.h>
#include <soc/soc_chip.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
@ -55,6 +56,11 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
enable_rtc_upper_bank();
if (CONFIG(IFWI_IBBM_LOAD)) {
load_ibb(CONFIG_IBBM_ROM_ADDR, CONFIG_IBBM_ROM_SIZE);
flush_l1d_to_l2();
}
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}