sb/intel/*/gpio: Convert get_gpios to gpio_base2_value

Drop the custom function to retrieve the value of multiple GPIOs
at once as integer value and use the generic function prototype
defined in include/gpio.h instead.

Therefore:
* select GENERIC_GPIO_LIB
* Stub gpio_input(). Existing code assumes the pin is input.
* Drop get_gpios() implementation
* Include new header file gpio.h
* Migrate pins from type int to gpio_t

Migrate all users of the old function to the new function.

Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.

Change-Id: I2296ff72231b569c618295b36b95a89ffebb3a6e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88503
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/auron/variants/auron_paine/spd/spd.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/google/auron/variant.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Auron board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
@@ -10,13 +10,12 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
-		SPD_GPIO_BIT2,
-		-1,
+		SPD_GPIO_BIT2
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)

src/mainboard/google/auron/variants/auron_yuna/spd/spd.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/google/auron/variant.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Auron board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
@@ -10,13 +10,12 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
-		SPD_GPIO_BIT2,
-		-1,
+		SPD_GPIO_BIT2
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)

src/mainboard/google/auron/variants/gandof/spd/spd.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/google/auron/variant.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Gandof board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
@@ -10,13 +10,12 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
-		SPD_GPIO_BIT2,
-		-1,
+		SPD_GPIO_BIT2
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)

src/mainboard/google/auron/variants/lulu/spd/spd.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/google/auron/variant.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Lulu board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		13
@@ -11,14 +11,13 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
 		SPD_GPIO_BIT2,
-		SPD_GPIO_BIT3,
-		-1,
+		SPD_GPIO_BIT3
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)

src/mainboard/google/auron/variants/samus/spd/spd.c

@@ -2,7 +2,7 @@
 
 #include <mainboard/google/auron/variant.h>
 #include <soc/pei_wrapper.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
+#include <gpio.h>
 
 /* Samus board memory configuration GPIOs */
 #define SPD_GPIO_BIT0		69
@@ -12,14 +12,13 @@
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {
+	const gpio_t gpio_vector[] = {
 		SPD_GPIO_BIT0,
 		SPD_GPIO_BIT1,
 		SPD_GPIO_BIT2,
-		SPD_GPIO_BIT3,
-		-1,
+		SPD_GPIO_BIT3
 	};
-	return get_gpios(gpio_vector);
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)

src/mainboard/google/link/early_init.c

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/pci_ops.h>
+#include <gpio.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include "ec/google/chromeec/ec.h"
 
 #include <southbridge/intel/bd82x6x/chip.h>
@@ -54,8 +54,8 @@ void mainboard_late_rcba_config(void)
 
 static unsigned int get_spd_index(void)
 {
-	const int gpio_vector[] = {41, 42, 43, 10, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {41, 42, 43, 10};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)

src/mainboard/google/slippy/variants/falco/romstage.c

@@ -1,14 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <gpio.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../variant.h"
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {13, 9, 47, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {13, 9, 47};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)

src/mainboard/google/slippy/variants/leon/romstage.c

@@ -1,14 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <gpio.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../variant.h"
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {13, 9, 47, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {13, 9, 47};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)

src/mainboard/google/slippy/variants/peppy/romstage.c

@@ -2,16 +2,16 @@
 
 #include <stdint.h>
 #include <ec/google/chromeec/ec.h>
+#include <gpio.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../onboard.h"
 #include "../../variant.h"
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {13, 9, 47, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {13, 9, 47};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)

src/mainboard/google/slippy/variants/wolf/romstage.c

@@ -1,14 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <gpio.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "../../variant.h"
 
 unsigned int variant_get_spd_index(void)
 {
-	const int gpio_vector[] = {13, 9, 47, -1};
-	return get_gpios(gpio_vector);
+	const gpio_t gpio_vector[] = {13, 9, 47};
+	return gpio_base2_value(gpio_vector, ARRAY_SIZE(gpio_vector));
 }
 
 bool variant_is_dual_channel(const unsigned int spd_index)

src/mainboard/lenovo/s230u/early_init.c

@@ -2,9 +2,9 @@
 
 #include <device/pci_ops.h>
 #include <console/console.h>
+#include <gpio.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 #include "ec.h"
 
 void mainboard_pch_lpc_setup(void)
@@ -34,9 +34,9 @@ static const char *mainboard_spd_names[9] = {
 
 static unsigned int get_spd_index(void)
 {
-	const int spd_gpios[] = {71, 70, 16, 48, -1};
+	const gpio_t spd_gpios[] = {71, 70, 16, 48};
 
-	unsigned int spd_index = get_gpios(spd_gpios);
+	unsigned int spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 	if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) {
 		/* Fallback to pessimistic 2GB image (ELPIDA 2GB) */
 		spd_index = 6;

src/mainboard/lenovo/t410/dock.c

@@ -2,6 +2,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <gpio.h>
 #include "dock.h"
 #include <southbridge/intel/common/gpio.h>
 #include <ec/lenovo/h8/h8.h>
@@ -35,7 +36,6 @@ void dock_disconnect(void)
 
 int dock_present(void)
 {
-	const int gpio_num_array[] = {3, 4, 5, -1};
-
-	return get_gpios(gpio_num_array) != 7;
+	const gpio_t gpio_num_array[] = {3, 4, 5};
+	return gpio_base2_value(gpio_num_array, ARRAY_SIZE(gpio_num_array)) != 7;
 }

src/mainboard/lenovo/x1_carbon_gen1/early_init.c

@@ -1,13 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
+#include <gpio.h>
 #include <northbridge/intel/sandybridge/raminit.h>
-#include <southbridge/intel/common/gpio.h>
 
 static unsigned int get_spd_index(void)
 {
-	const int spd_gpio_vector[] = {25, 45, -1};
-	unsigned int spd_index = get_gpios(spd_gpio_vector);
+	const gpio_t spd_gpio_vector[] = {25, 45};
+	unsigned int spd_index = gpio_base2_value(spd_gpio_vector,
+						  ARRAY_SIZE(spd_gpio_vector));
 
 	/* 4gb model = 0, 8gb model = 1 */
 	/* int extended_memory_version = gpio_get(44); */

src/mainboard/lenovo/x200/variants/x200/dock.c

@@ -2,6 +2,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <gpio.h>
 #include <southbridge/intel/common/gpio.h>
 #include <ec/lenovo/h8/h8.h>
 #include <ec/acpi/ec.h>
@@ -32,7 +33,7 @@ void dock_disconnect(void)
 
 int dock_present(void)
 {
-	const int dock_id_gpio[] = { 2, 3, 4, -1};
+	const gpio_t dock_id_gpio[] = {2, 3, 4};
 
-	return get_gpios(dock_id_gpio) != 7;
+	return gpio_base2_value(dock_id_gpio, ARRAY_SIZE(dock_id_gpio)) != 7;
 }

src/mainboard/lenovo/x201/dock.c

@@ -2,6 +2,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <gpio.h>
 #include "dock.h"
 #include <southbridge/intel/common/gpio.h>
 #include <ec/lenovo/h8/h8.h>
@@ -37,7 +38,7 @@ void dock_disconnect(void)
 
 int dock_present(void)
 {
-	const int dock_id_gpio[] = { 3, 4, 5, -1};
+	const gpio_t dock_id_gpio[] = {3, 4, 5};
 
-	return get_gpios(dock_id_gpio) != 7;
+	return gpio_base2_value(dock_id_gpio, ARRAY_SIZE(dock_id_gpio)) != 7;
 }

src/soc/intel/broadwell/Kconfig

@@ -4,6 +4,7 @@ config SOC_INTEL_BROADWELL
 	bool
 	select CACHE_MRC_SETTINGS
 	select CPU_INTEL_HASWELL
+	select GENERIC_GPIO_LIB
 	select INTEL_GMA_ACPI
 	select MRC_SETTINGS_PROTECT
 	select REG_SCRIPT

src/southbridge/intel/common/Kconfig.common

@@ -15,6 +15,7 @@ config SOUTHBRIDGE_INTEL_COMMON_PMBASE
 	def_bool n
 
 config SOUTHBRIDGE_INTEL_COMMON_GPIO
+	select GENERIC_GPIO_LIB
 	def_bool n
 
 config SOUTHBRIDGE_INTEL_COMMON_ME

src/southbridge/intel/common/gpio.c

@@ -1,10 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include <device/pci_type.h>
 #include <gpio.h>
 #include <stdint.h>
+#include <gpio.h>
 
 #include "southbridge/intel/common/gpio.h"
 
@@ -100,25 +102,6 @@ int gpio_get(gpio_t gpio_num)
 	return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1;
 }
 
-/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned int get_gpios(const int *gpio_num_array)
-{
-	int gpio;
-	unsigned int bitmask = 1;
-	unsigned int vector = 0;
-
-	while (bitmask &&
-	       ((gpio = *gpio_num_array++) != -1)) {
-		if (gpio_get(gpio))
-			vector |= bitmask;
-		bitmask <<= 1;
-	}
-	return vector;
-}
-
 /*
  * set gpio output to level.
  */
@@ -162,3 +145,8 @@ int gpio_is_native(int gpio_num)
 	config = inl(gpio_base + gpio_reg_offsets[index]);
 	return !(config & (1 << bit));
 }
+
+void gpio_input(gpio_t gpio)
+{
+	// FIXME: Implement
+}

src/southbridge/intel/common/gpio.h

@@ -151,12 +151,6 @@ extern const struct pch_gpio_map mainboard_gpio_map;
 /* Configure GPIOs with mainboard provided settings */
 void setup_pch_gpios(const struct pch_gpio_map *gpio);
 
-/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned int get_gpios(const int *gpio_num_array);
-
 void set_gpio(int gpio_num, int value);
 
 void clear_gpio(int gpio_num);

src/southbridge/intel/lynxpoint/Kconfig

@@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_LYNXPOINT
 	select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
 	select RTC
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
+	select GENERIC_GPIO_LIB
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
 	select HAVE_POWER_STATE_AFTER_FAILURE

src/southbridge/intel/lynxpoint/lp_gpio.c

@@ -110,25 +110,6 @@ int gpio_get(gpio_t gpio_num)
 	return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
 }
 
-/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned int get_gpios(const int *gpio_num_array)
-{
-	int gpio;
-	unsigned int bitmask = 1;
-	unsigned int vector = 0;
-
-	while (bitmask &&
-	       ((gpio = *gpio_num_array++) != -1)) {
-		if (gpio_get(gpio))
-			vector |= bitmask;
-		bitmask <<= 1;
-	}
-	return vector;
-}
-
 void set_gpio(int gpio_num, int value)
 {
 	u16 gpio_base = get_gpio_base();
@@ -149,3 +130,8 @@ int gpio_is_native(int gpio_num)
 
 	return !(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & 1);
 }
+
+void gpio_input(gpio_t gpio)
+{
+	// FIXME: Implement
+}

src/southbridge/intel/lynxpoint/lp_gpio.h

@@ -163,12 +163,6 @@ void set_gpio(int gpio_num, int value);
 /* Return non-zero if gpio is set to native function. 0 otherwise. */
 int gpio_is_native(int gpio_num);
 
-/*
- * Get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned int get_gpios(const int *gpio_num_array);
-
 extern const struct pch_lp_gpio_map mainboard_lp_gpio_map[];
 
 #endif