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soc/intel/pantherlake: Configure FSP UPDs for minimum assertion widths

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This configures FSP UPDs for PCH PM minimum assertion widths and
reset power cycle duration per mainboard variants configuration.
This also checks the reset power cycle duration is not be smaller
than SLP_S3, SLP_S4 and SLP_A Minimum Assertion Width.

 PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
 PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
 PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
 PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
 PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
  The Reset Power Cycle Duration starts at 20ms and increases by 20ms
  for each step, beginning from 0x0 to 0xFF. Each subsequent increment
  corresponds to an additional 20 milliseconds in duration.

Reference:
 Panther Lake External Design Specification (EDS) Volume 2 (#813032)

BUG=None
TEST=Build a fatcat coreboot and boot to OS without an issue.

Change-Id: I7234c7539c1e7eb5e2b8c04ccff6c62c853d6807
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88443
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jamie Ryu 2025-04-28 00:25:12 -07:00 • committed by Matt DeVillier
commit e9af95d5ab
2 changed files with 101 additions and 0 deletions
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56
src/soc/intel/pantherlake/chip.h
View file

@ -521,6 +521,62 @@ struct soc_intel_pantherlake_config {
ISA_SERIAL_BASE_ADDR_2F8,
} isa_serial_uart_base;
/* PCH PM SLP_S3 Minimum Assertion Width */
enum {
SLP_S3_ASSERTION_DEFAULT,
SLP_S3_ASSERTION_60_US,
SLP_S3_ASSERTION_1_MS,
SLP_S3_ASSERTION_50_MS,
SLP_S3_ASSERTION_2_S,
} pch_slp_s3_min_assertion_width;
/* PCH PM SLP_S4 Minimum Assertion Width */
enum {
SLP_S4_ASSERTION_DEFAULT,
SLP_S4_ASSERTION_1S,
SLP_S4_ASSERTION_2S,
SLP_S4_ASSERTION_3S,
SLP_S4_ASSERTION_4S,
} pch_slp_s4_min_assertion_width;
/* PCH PM SLP_SUS Minimum Assertion Width */
enum {
SLP_SUS_ASSERTION_DEFAULT,
SLP_SUS_ASSERTION_0_MS,
SLP_SUS_ASSERTION_500_MS,
SLP_SUS_ASSERTION_1_S,
SLP_SUS_ASSERTION_4_S,
} pch_slp_sus_min_assertion_width;
/* PCH PM SLP_A Minimum Assertion Width */
enum {
SLP_A_ASSERTION_DEFAULT,
SLP_A_ASSERTION_0_MS,
SLP_A_ASSERTION_4_S,
SLP_A_ASSERTION_98_MS,
SLP_A_ASSERTION_2_S,
} pch_slp_a_min_assertion_width;
/*
* PCH PM Reset Power Cycle Duration
* The Reset Power Cycle Duration starts at 20ms and increases by 20ms for each step,
* beginning from 0x0 in hexadecimal. Each subsequent hexadecimal increment corresponds
* to an additional 20 milliseconds in duration.
* NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
* stretch duration programmed in the following registers:
* - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
* - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
* - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
* - PM_CFG.SLP_LAN_MIN_ASST_WDTH
*/
enum {
POWER_CYCLE_DURATION_DEFAULT,
POWER_CYCLE_DURATION_1S,
POWER_CYCLE_DURATION_2S,
POWER_CYCLE_DURATION_3S,
POWER_CYCLE_DURATION_4S,
} pch_reset_power_cycle_duration;
/*
* Enable or Disable C1 C-state Auto Demotion & un-demotion
* The algorithm looks at the behavior of the wake up tracker, how

45
src/soc/intel/pantherlake/fsp_params.c
View file

@ -10,6 +10,7 @@
#include <fsp/ppi/mp_service_ppi.h>
#include <intelblocks/irq.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
@ -663,6 +664,50 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
/* Enable/Disable PCH to CPU energy report feature. */
s_cfg->PchPmDisableEnergyReport = !config->pch_pm_energy_report_enable;
/* Apply PCH PM minimum assertion width settings */
if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT)
s_cfg->PchPmSlpS3MinAssert = SLP_S3_ASSERTION_50_MS;
else
s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width;
if (config->pch_slp_s4_min_assertion_width == SLP_S4_ASSERTION_DEFAULT)
s_cfg->PchPmSlpS4MinAssert = SLP_S4_ASSERTION_1S;
else
s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width;
if (config->pch_slp_sus_min_assertion_width == SLP_SUS_ASSERTION_DEFAULT)
s_cfg->PchPmSlpSusMinAssert = SLP_SUS_ASSERTION_4_S;
else
s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width;
if (config->pch_slp_a_min_assertion_width == SLP_A_ASSERTION_DEFAULT)
s_cfg->PchPmSlpAMinAssert = SLP_A_ASSERTION_2_S;
else
s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width;
/*
* The Reset Power Cycle Duration starts at 20ms and increases by 20ms for each step,
* beginning from 0x0 to 0xFF. Each subsequent increment corresponds to an additional
* 20 milliseconds in duration.
* PCH PM Reset Power Cycle Duration = (PchPmPwrCycDur + 1) * 20ms
*/
const uint8_t fsp_pm_pwr_cyc_dur_list[] = {
0xc7, /* POWER_CYCLE_DURATION_DEFAULT */
0x31, /* POWER_CYCLE_DURATION_1S */
0x63, /* POWER_CYCLE_DURATION_2S */
0x95, /* POWER_CYCLE_DURATION_3S */
0xc7 /* POWER_CYCLE_DURATION_4S */
};
if (config->pch_reset_power_cycle_duration) {
uint8_t pwr_cyc_dur = get_pm_pwr_cyc_dur(s_cfg->PchPmSlpS4MinAssert,
s_cfg->PchPmSlpS3MinAssert,
s_cfg->PchPmSlpAMinAssert,
config->pch_reset_power_cycle_duration);
s_cfg->PchPmPwrCycDur = fsp_pm_pwr_cyc_dur_list[pwr_cyc_dur];
} else {
s_cfg->PchPmPwrCycDur = fsp_pm_pwr_cyc_dur_list[POWER_CYCLE_DURATION_DEFAULT];
}
}
static void fill_fsps_npu_params(FSP_S_CONFIG *s_cfg,