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soc/intel/xeon_sp: Remove fast_spi_cache_bios_region

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FSP-T will help to cache bios region along with MTRR programming
by setting CodeRegionBase/CodeRegionLength, thus there is no need
for xeon_sp platforms to do it.

TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/archercity CRB

Check MTRR usage and below duplicated MTRR item get removed:
[DEBUG]  0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP
[DEBUG]  0x000fffffff000800: PHYMASK1: Length  = 0x0000000001000000, Valid

Change-Id: Ia414a35c663f3aa1b02d944475a96e11d07a4f00
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit is contained in:
Jincheng Li 2025-07-21 18:16:12 +08:00 • committed by Matt DeVillier
commit 85b26f75d2
1 changed files with 1 additions and 2 deletions
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3
src/soc/intel/xeon_sp/bootblock.c
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@ -73,14 +73,13 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
*/
assembly_timestamp = base_timestamp;
bootblock_timestamp = timestamp_get();
fast_spi_early_init(SPI_BASE_ADDRESS);
fast_spi_cache_bios_region();
bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp));
}
void bootblock_soc_early_init(void)
{
fast_spi_early_init(SPI_BASE_ADDRESS);
pch_enable_lpc();
/* Set up P2SB BAR. This is needed for PCR to work */