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soc/intel/xeon_sp/ibl: Config ACPI base using PMC device

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IBL shall use PMC device to program ABASE instead of PCR.

TESTED=Build and boot on intel/avenuecity CRB with below log:
[INFO ]  soc_config_acpibase : pmbase = 501

Change-Id: I3497c287a5370deed02b269405bc45d5d41e7f33
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88144
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jincheng Li 2025-06-18 09:47:02 +08:00 • committed by Matt DeVillier
commit a87cbcd3c9
1 changed files with 10 additions and 22 deletions
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32
src/soc/intel/xeon_sp/ibl/soc_pch.c
View file

@ -1,40 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <intelblocks/pcr.h>
#include <soc/bootblock.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pmc.h>
#include <soc/soc_pch.h>
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x600
#define PCR_PSFX_TO_SHDW_BAR4 0x10
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
static void soc_config_acpibase(void)
{
uint32_t pmc_reg_value;
uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
/* Disable IO command in PMC Device first before changing Base Address */
uint16_t reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
pci_write_config16(PCH_DEV_PMC, PCI_COMMAND,
reg16 & ~(PCI_COMMAND_IO | PCI_COMMAND_MASTER));
pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
/* Program ACPI Base */
pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS);
if (pmc_reg_value != 0xffffffff) {
/* Disable Io Space before changing the address */
pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
/* Program ABASE in PSF3 PMC space BAR4*/
pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
ACPI_BASE_ADDRESS);
/* Enable IO Space */
pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
}
/* Enable Bus Master and IO Space */
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_IO | PCI_COMMAND_MASTER));
uint16_t data = pcr_read16(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE);
assert(ACPI_BASE_ADDRESS == (data & ~PCI_BASE_ADDRESS_IO_ATTR_MASK));
printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data);
}