tree: Use boolean for PcieRpSlotImplemented[]

Change-Id: I15b062a7225700988d5db8a0840d555dc2a1c353
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88269
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/asrock/imb-1222/devicetree.cb

@@ -224,7 +224,7 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4)
 			register "PcieRpLtrEnable[16]" = "true"
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X"
@@ -235,14 +235,14 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1)
-			register "PcieRpSlotImplemented[5]" = "1"
+			register "PcieRpSlotImplemented[5]" = "true"
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1)
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieClkSrcUsage[6]" = "6"
 			register "PcieClkSrcClkReq[6]" = "6"

src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb

@@ -121,21 +121,21 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13 on
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref lpc_espi on

src/mainboard/erying/tgl/devicetree.cb

@@ -109,13 +109,13 @@ chip soc/intel/tigerlake
 		end
 
 		device ref pcie_rp5 on		# PCH M.2 (Gen3)
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 			register "PcieClkSrcUsage[4]" = "4"
 			register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
 		end
 
 		device ref pcie_rp9 on		# PCH NGFF (WiFi)
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			register "PcieClkSrcUsage[5]" = "8"
 			register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
 
@@ -127,7 +127,7 @@ chip soc/intel/tigerlake
 		end
 
 		device ref pcie_rp12 on		# PCH x1 (Gen3)
-			register "PcieRpSlotImplemented[11]" = "1"
+			register "PcieRpSlotImplemented[11]" = "true"
 			register "PcieClkSrcUsage[1]" = "11"
 			register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
 		end

src/mainboard/google/drallion/variants/drallion/devicetree.cb

@@ -408,11 +408,11 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9 on
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp13 on
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 		end
 		device ref uart0 on end
 		device ref lpc_espi on

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -282,14 +282,14 @@ chip soc/intel/cannonlake
 		device ref sata		on end
 		device ref i2c4		on end
 		device ref pcie_rp9	on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end # (x4 NVMe)
 		device ref pcie_rp14	on
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_DW1_01"
 				device generic 0 on  end
 			end
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 		end # (x1 WiFi)
 		device ref uart0	on end
 		device ref gspi0	on

src/mainboard/google/puff/variants/ambassador/overridetree.cb

@@ -388,11 +388,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 

src/mainboard/google/puff/variants/baseboard/devicetree.cb

@@ -284,7 +284,7 @@ chip soc/intel/cannonlake
 		device ref sata		on end
 		device ref pcie_rp9	on
 			# X4 NVME
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp14	on
 			# x4
@@ -292,7 +292,7 @@ chip soc/intel/cannonlake
 				register "wake" = "GPE0_DW1_01"
 				device generic 0 on  end
 			end
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 		end
 		device ref uart0	on end
 		device ref gspi0	on

src/mainboard/google/puff/variants/dooly/overridetree.cb

@@ -385,7 +385,7 @@ chip soc/intel/cannonlake
 		device ref emmc		on end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 		device ref hda		on
 			chip drivers/sof

src/mainboard/google/puff/variants/duffy/overridetree.cb

@@ -447,11 +447,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 

src/mainboard/google/puff/variants/faffy/overridetree.cb

@@ -421,11 +421,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 

src/mainboard/google/puff/variants/genesis/overridetree.cb

@@ -412,23 +412,23 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8	on
 			# WLAN
-			register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[7]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp9	on
 			# TPU
-			register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[8]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp11	on
 			# TPU1
-			register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[10]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp12	on
 			# TPU0
-			register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[11]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp13	on
 			# X4 i350 NIC
-			register "PcieRpSlotImplemented[12]" = "0" # Built-in
+			register "PcieRpSlotImplemented[12]" = "false" # Built-in
 		end
 	end
 

src/mainboard/google/puff/variants/kaisa/overridetree.cb

@@ -447,11 +447,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 

src/mainboard/google/puff/variants/moonbuggy/overridetree.cb

@@ -414,23 +414,23 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8	on
 			# WLAN
-			register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[7]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp9	on
 			# TPU
-			register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[8]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp11	on
 			# TPU1
-			register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[10]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp12	on
 			# TPU0
-			register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[11]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp13	on
 			# X4 i350 NIC
-			register "PcieRpSlotImplemented[12]" = "0" # Built-in
+			register "PcieRpSlotImplemented[12]" = "false" # Built-in
 		end
 		device ref uart1	on end
 	end

src/mainboard/google/puff/variants/noibat/overridetree.cb

@@ -358,11 +358,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 

src/mainboard/google/puff/variants/puff/overridetree.cb

@@ -382,11 +382,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device pci 00.0 on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 

src/mainboard/google/puff/variants/scout/overridetree.cb

@@ -397,19 +397,19 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp8	on
 			# WLAN
-			register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[7]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp9	on
 			# SSD
-			register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[8]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp13	on
 			# TPU0
-			register "PcieRpSlotImplemented[12]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[12]" = "true" # M.2 Slot
 		end
 		device ref pcie_rp14	on
 			# TPU1
-			register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot
+			register "PcieRpSlotImplemented[13]" = "true" # M.2 Slot
 		end
 		device ref uart1	on end
 	end

src/mainboard/google/puff/variants/wyvern/overridetree.cb

@@ -383,11 +383,11 @@ chip soc/intel/cannonlake
 				register "enable_aspm_l1_2" = "1"
 				device ref system_agent on end
 			end
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp11	on
 			# X2 NVMe
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 	end
 

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -338,10 +338,10 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref pcie_rp10 on
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
-			register "PcieRpSlotImplemented[9]" = "1"
+			register "PcieRpSlotImplemented[9]" = "true"
 		end
 		device ref pcie_rp11 on
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 		device ref pcie_rp13 on
 			# x4 lanes
@@ -350,7 +350,7 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 		end
 		device ref lpc_espi on
 			chip ec/google/wilco

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -365,10 +365,10 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref pcie_rp1 on
 			# USB
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp8 on
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 		end
 		device ref pcie_rp9 on
 			chip drivers/generic/bayhub
@@ -376,10 +376,10 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp10 on
-			register "PcieRpSlotImplemented[9]" = "1"
+			register "PcieRpSlotImplemented[9]" = "true"
 		end
 		device ref pcie_rp13 on
 			# x4 lanes
@@ -388,7 +388,7 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 		end
 		device ref lpc_espi on
 			chip ec/google/wilco

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -428,7 +428,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieClkSrcUsage[1]" = "6"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp8 on
 			# SD Card PCIE 8 using clk 3
@@ -467,13 +467,13 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[0]" = "8"
 			register "PcieClkSrcClkReq[0]" = "0"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp11 on
 			# Optane PCIE 11 using clk 0
 			register "PcieRpLtrEnable[10]" = "true"
 			register "HybridStorageMode" = "0"
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 		end
 		device ref uart0 on end
 		device ref gspi0 on

src/mainboard/google/volteer/variants/voema/overridetree.cb

@@ -92,7 +92,7 @@ chip soc/intel/tigerlake
 			# Disable WLAN PCIE 7
 			register "PcieRpLtrEnable[6]" = "false"
 			register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 		end
 		device ref pcie_rp8 off
 			# Disable SD Card PCIE 8

src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb

@@ -67,13 +67,13 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on	# x1 SLOT2/LAN
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref gbe on  end
 	end

src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb

@@ -77,28 +77,28 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on	# x4 SLOT 1
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp17 on
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 		end
 		device ref pcie_rp18 on
-			register "PcieRpSlotImplemented[17]" = "1"
+			register "PcieRpSlotImplemented[17]" = "true"
 		end
 		device ref pcie_rp19 on
-			register "PcieRpSlotImplemented[18]" = "1"
+			register "PcieRpSlotImplemented[18]" = "true"
 		end
 		device ref pcie_rp20 on
-			register "PcieRpSlotImplemented[19]" = "1"
+			register "PcieRpSlotImplemented[19]" = "true"
 		end
 		device ref pcie_rp21 on	# x4 SLOT 2
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 		end
 		device ref gbe on  end
 	end

src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb

@@ -61,13 +61,13 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on	# x1 SLOT2/LAN
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 	end
 end

src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb

@@ -73,13 +73,13 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on	# x1 SLOT2/LAN
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref gbe on  end
 	end

src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb

@@ -57,13 +57,13 @@ chip soc/intel/cannonlake
 		device ref uart2 on  end
 		device ref emmc on  end
 		device ref pcie_rp1 on	# x4 SLOT1
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 		end
 		device ref pcie_rp5 on	# x1 SLOT2/LAN
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref gbe on  end
 	end

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -242,13 +242,13 @@ chip soc/intel/tigerlake
 		device ref pcie_rp1 off end
 		device ref pcie_rp2 off end
 		device ref pcie_rp3 on
-			register "PcieRpSlotImplemented[2]" = "1"
+			register "PcieRpSlotImplemented[2]" = "true"
 			register "PcieRpLtrEnable[2]" = "true"
 			register "PcieClkSrcUsage[1]" = "0x2"
 			register "PcieClkSrcClkReq[1]" = "1"
 		end
 		device ref pcie_rp4 on
-			register "PcieRpSlotImplemented[3]" = "1"
+			register "PcieRpSlotImplemented[3]" = "true"
 			register "PcieRpLtrEnable[3]" = "true"
 			register "PcieClkSrcUsage[2]" = "0x3"
 			register "PcieClkSrcClkReq[2]" = "2"
@@ -263,14 +263,14 @@ chip soc/intel/tigerlake
 		device ref pcie_rp7 off end
 		device ref pcie_rp8 off end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "0x8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10 off end
 		device ref pcie_rp11 on
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 			register "PcieRpLtrEnable[10]" = "true"
 		end
 		device ref pcie_rp12 off end

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

@@ -244,14 +244,14 @@ chip soc/intel/tigerlake
 		device ref pcie_rp1 off end
 		device ref pcie_rp2 off end
 		device ref pcie_rp3 on
-			register "PcieRpSlotImplemented[2]" = "1"
+			register "PcieRpSlotImplemented[2]" = "true"
 			register "PcieRpLtrEnable[2]" = "true"
 			register "PcieClkSrcUsage[1]" = "0x2"
 			register "PcieClkSrcClkReq[1]" = "1"
 		end
 
 		device ref pcie_rp4 on
-			register "PcieRpSlotImplemented[3]" = "1"
+			register "PcieRpSlotImplemented[3]" = "true"
 			register "PcieRpLtrEnable[3]" = "true"
 			register "PcieClkSrcUsage[2]" = "0x3"
 			register "PcieClkSrcClkReq[2]" = "2"
@@ -266,14 +266,14 @@ chip soc/intel/tigerlake
 		device ref pcie_rp7 off end
 		device ref pcie_rp8 off end
 		device ref pcie_rp9 on
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[3]" = "0x8"
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp10 off end
 		device ref pcie_rp11 on
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 			register "PcieRpLtrEnable[10]" = "true"
 		end
 		device ref pcie_rp12 off end

src/mainboard/lenovo/m920q/devicetree.cb

@@ -67,25 +67,25 @@ chip soc/intel/cannonlake
 		end
 
 		device ref pcie_rp6	on # WLAN
-			register "PcieRpSlotImplemented[5]"	= "1"
+			register "PcieRpSlotImplemented[5]"	= "true"
 			register "PcieClkSrcUsage[3]"		= "5"
 			register "PcieClkSrcClkReq[3]"		= "3"
 		end
 
 		device ref pcie_rp9	on # PCIe x4
-			register "PcieRpSlotImplemented[8]"	= "1"
+			register "PcieRpSlotImplemented[8]"	= "true"
 			register "PcieClkSrcUsage[2]"		= "8"
 			register "PcieClkSrcClkReq[2]"		= "2"
 		end
 
 		device ref pcie_rp17 on # M.2 SSD #2
-			register "PcieRpSlotImplemented[16]"	= "1"
+			register "PcieRpSlotImplemented[16]"	= "true"
 			register "PcieClkSrcUsage[10]"		= "16"
 			register "PcieClkSrcClkReq[10]"		= "10"
 		end
 
 		device ref pcie_rp21 on # M.2 SSD #1
-			register "PcieRpSlotImplemented[20]"	= "1"
+			register "PcieRpSlotImplemented[20]"	= "true"
 			register "PcieClkSrcUsage[4]"		= "20"
 			register "PcieClkSrcClkReq[4]"		= "4"
 		end

src/mainboard/prodrive/hermes/devicetree.cb

@@ -172,7 +172,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp21 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
 			register "PcieRpLtrEnable[20]" = "true"
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
 			register "PcieRpAdvancedErrorReporting[20]" = "1"
 			register "PcieRpAspm[20]" = "AspmDisabled"
@@ -180,7 +180,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp1 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
 			register "PcieRpLtrEnable[0]" = "true"
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 			register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
 			register "PcieRpAdvancedErrorReporting[0]" = "1"
 			register "PcieRpAspm[0]" = "AspmDisabled"
@@ -212,7 +212,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp9 on
 			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
 			register "PcieRpLtrEnable[8]" = "true"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 		end
 		device ref pcie_rp14 on	# PHY 0
 			register "PcieRpLtrEnable[13]" = "true"
@@ -225,12 +225,12 @@ chip soc/intel/cannonlake
 				device pci 00.0 on end  # Aspeed 2500 VGA
 			end
 			register "PcieRpLtrEnable[14]" = "true"
-			register "PcieRpSlotImplemented[14]" = "1"
+			register "PcieRpSlotImplemented[14]" = "true"
 		end
 		device ref pcie_rp16 on	# M.2 E/CNVi
 			# Disabled when CNVi is present
 			register "PcieRpLtrEnable[15]" = "true"
-			register "PcieRpSlotImplemented[15]" = "1"
+			register "PcieRpSlotImplemented[15]" = "true"
 		end
 		device ref uart0 on  end
 		device ref uart1 on  end

src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb

@@ -125,7 +125,7 @@ chip soc/intel/cannonlake
 			register "SataPortsDevSlp[2]" = "1"
 		end
 		device ref pcie_rp7 on	# x1 M.2/E 2230 (WLAN)
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 			register "PcieRpLtrEnable[6]" = "true"
 			register "PcieRpHotPlug[6]" = "1"
 			register "PcieClkSrcUsage[2]" = "6"
@@ -138,14 +138,14 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp9 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[0]" = "8"
 			register "PcieClkSrcClkReq[0]" = "0"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[1]" = "12"
 			register "PcieClkSrcClkReq[1]" = "1"

src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb

@@ -117,7 +117,7 @@ chip soc/intel/cannonlake
 			register "satapwroptimize" = "1"
 		end
 		device ref pcie_rp8 on	# x1 M.2/E 2230 (WLAN)
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			register "PcieRpLtrEnable[7]" = "true"
 			# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
 			register "PcieClkSrcUsage[2]" = "0x80"
@@ -129,7 +129,7 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcClkReq[3]" = "3"
 		end
 		device ref pcie_rp13 on	# x4 M.2/M 2280 (NVMe)
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[1]" = "12"
 			register "PcieClkSrcClkReq[1]" = "1"

src/mainboard/purism/librem_l1um_v2/devicetree.cb

@@ -209,13 +209,13 @@ chip soc/intel/cannonlake
 			register "SataPortsHotPlug[7]" = "1"
 		end
 		device ref pcie_rp21 on
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[10]" = "20"
 			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp1 on
-			register "PcieRpSlotImplemented[0]" = "1"
+			register "PcieRpSlotImplemented[0]" = "true"
 			register "PcieRpLtrEnable[0]" = "true"
 			register "PcieClkSrcUsage[1]" = "0x80"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X"

src/mainboard/siemens/chili/variants/base/devicetree.cb

@@ -40,22 +40,22 @@ chip soc/intel/cannonlake
 			device pci 00.0 on end	# x1 i219
 			register "PcieClkSrcUsage[4]" = "0x70"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[4]" = "0"
+			register "PcieRpSlotImplemented[4]" = "false"
 		end
 		device ref pcie_rp6		on
 			device pci 00.0 on end	# x1 i210
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[5]" = "0"
+			register "PcieRpSlotImplemented[5]" = "false"
 		end
 		device ref pcie_rp7		on
-			register "PcieRpSlotImplemented[6]" = "1"
+			register "PcieRpSlotImplemented[6]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp17		on
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
 		end
 		device ref lpc_espi		on

src/mainboard/siemens/chili/variants/chili/devicetree.cb

@@ -87,30 +87,30 @@ chip soc/intel/cannonlake
 		device ref pcie_rp5		on
 			register "PcieClkSrcUsage[4]" = "4"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[4]" = "1"
+			register "PcieRpSlotImplemented[4]" = "true"
 		end
 		device ref pcie_rp6		on
 			device pci 00.0 on end	# i210 (x1)
 			register "PcieClkSrcUsage[5]" = "5"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[5]" = "0"
+			register "PcieRpSlotImplemented[5]" = "false"
 		end
 		device ref pcie_rp7		on
 			device pci 00.0 on end	# VL805 Front Rack/UIB (x1)
 			register "PcieClkSrcUsage[1]" = "6"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[6]" = "0"
+			register "PcieRpSlotImplemented[6]" = "false"
 		end
 		device ref pcie_rp8		on
 			device pci 00.0 on end	# VL805 Back MB (x1)
 			register "PcieClkSrcUsage[0]" = "7"
 			register "PcieClkSrcClkReq[0]" = "0"
-			register "PcieRpSlotImplemented[7]" = "0"
+			register "PcieRpSlotImplemented[7]" = "false"
 		end
 		device ref pcie_rp17		on
 			register "PcieClkSrcUsage[7]" = "16"
 			register "PcieClkSrcClkReq[7]" = "7"
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
 		end
 		device ref uart0		on  end

src/mainboard/starlabs/starbook/variants/cml/devicetree.cb

@@ -161,7 +161,7 @@ chip soc/intel/cannonlake
 		device ref i2c4 on  end
 		device ref uart2 on  end
 		device ref pcie_rp9 on						# SSD x4
-			register "PcieRpSlotImplemented[8]"	= "1"
+			register "PcieRpSlotImplemented[8]"	= "true"
 			register "PcieRpLtrEnable[8]"		= "true"
 			register "PcieClkSrcUsage[1]"		= "0x08"
 			register "PcieClkSrcClkReq[1]"		= "1"

src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb

@@ -182,7 +182,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]"			= "1"
 			register "PcieClkSrcUsage[3]"			= "0x08"
 			register "PcieClkSrcClkReq[3]"			= "3"
-			register "PcieRpSlotImplemented[8]"		= "1"
+			register "PcieRpSlotImplemented[8]"		= "true"
 
 			smbios_slot_desc				"SlotTypeM2Socket3"
 									"SlotLengthOther"

src/mainboard/system76/addw1/devicetree.cb

@@ -106,7 +106,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[10]" = "20"
 			register "PcieClkSrcClkReq[10]" = "10"
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
@@ -114,7 +114,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
@@ -122,21 +122,21 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[5]" = "13"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 7 (Card Reader)
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[7]" = "14"
 			register "PcieClkSrcClkReq[7]" = "7"
-			register "PcieRpSlotImplemented[14]" = "1"
+			register "PcieRpSlotImplemented[14]" = "true"
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 6 (WLAN)
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"
-			register "PcieRpSlotImplemented[15]" = "1"
+			register "PcieRpSlotImplemented[15]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref lpc_espi	on

src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb

@@ -44,14 +44,14 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[5]" = "true"
 			register "PcieClkSrcUsage[3]" = "5"
 			register "PcieClkSrcClkReq[3]" = "3"
-			register "PcieRpSlotImplemented[5]" = "1"
+			register "PcieRpSlotImplemented[5]" = "true"
 		end
 		device ref pcie_rp8	on
 			device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			chip drivers/wifi/generic
 				device pci 00.0 on end
 			end
@@ -62,7 +62,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp13	on
@@ -70,7 +70,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[12]" = "true"
 			register "PcieClkSrcUsage[5]" = "12"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[12]" = "1"
+			register "PcieRpSlotImplemented[12]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 	end

src/mainboard/system76/gaze15/devicetree.cb

@@ -97,7 +97,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
@@ -105,7 +105,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
@@ -113,7 +113,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[6]" = "13"
 			register "PcieClkSrcClkReq[6]" = "6"
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp15	on
@@ -121,7 +121,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[5]" = "14"
 			register "PcieClkSrcClkReq[5]" = "5"
-			register "PcieRpSlotImplemented[14]" = "1"
+			register "PcieRpSlotImplemented[14]" = "true"
 		end
 		device ref lpc_espi	on
 			register "gen1_dec" = "0x00040069"

src/mainboard/system76/oryp6/devicetree.cb

@@ -108,14 +108,14 @@ chip soc/intel/cannonlake
 			register "PcieRpHotPlug[16]" = "1"
 			register "PcieClkSrcUsage[0]" = "16"
 			register "PcieClkSrcClkReq[0]" = "0"
-			register "PcieRpSlotImplemented[16]" = "1"
+			register "PcieRpSlotImplemented[16]" = "true"
 		end
 		device ref pcie_rp21	on
 			# PCI Express root port #21 x4, Clock 11 (SSD2)
 			register "PcieRpLtrEnable[20]" = "true"
 			register "PcieClkSrcUsage[11]" = "20"
 			register "PcieClkSrcClkReq[11]" = "11"
-			register "PcieRpSlotImplemented[20]" = "1"
+			register "PcieRpSlotImplemented[20]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp9	on
@@ -123,7 +123,7 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[12]" = "8"
 			register "PcieClkSrcClkReq[12]" = "12"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 		device ref pcie_rp14	on
@@ -131,21 +131,21 @@ chip soc/intel/cannonlake
 			register "PcieRpLtrEnable[13]" = "true"
 			register "PcieClkSrcUsage[7]" = "13"
 			register "PcieClkSrcClkReq[7]" = "7"
-			register "PcieRpSlotImplemented[13]" = "1"
+			register "PcieRpSlotImplemented[13]" = "true"
 		end
 		device ref pcie_rp15	on
 			# PCI Express root port #15 x1, Clock 9 (Card Reader)
 			register "PcieRpLtrEnable[14]" = "true"
 			register "PcieClkSrcUsage[9]" = "14"
 			register "PcieClkSrcClkReq[9]" = "9"
-			register "PcieRpSlotImplemented[14]" = "1"
+			register "PcieRpSlotImplemented[14]" = "true"
 		end
 		device ref pcie_rp16	on
 			# PCI Express root port #16 x1, Clock 6 (WLAN)
 			register "PcieRpLtrEnable[15]" = "true"
 			register "PcieClkSrcUsage[6]" = "15"
 			register "PcieClkSrcClkReq[6]" = "6"
-			register "PcieRpSlotImplemented[15]" = "1"
+			register "PcieRpSlotImplemented[15]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref lpc_espi	on

src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb

@@ -71,7 +71,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[8]" = "7"
 			register "PcieClkSrcClkReq[8]" = "8"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
@@ -79,7 +79,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[9]" = "8"
 			register "PcieClkSrcClkReq[9]" = "9"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 		end
 	end

src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb

@@ -71,7 +71,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
@@ -79,7 +79,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[10]" = "8"
 			register "PcieClkSrcClkReq[10]" = "10"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref gbe on end

src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb

@@ -80,7 +80,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[2]" = "7"
 			register "PcieClkSrcClkReq[2]" = "2"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
@@ -88,7 +88,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[6]" = "8"
 			register "PcieClkSrcClkReq[6]" = "6"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
 		end
 		device ref smbus on

src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb

@@ -165,7 +165,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[7]" = "true"
 			register "PcieClkSrcUsage[1]" = "7"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[7]" = "1"
+			register "PcieRpSlotImplemented[7]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp9 on
@@ -173,7 +173,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[4]" = "8"
 			register "PcieClkSrcClkReq[4]" = "4"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD_PWR_EN
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3

src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb

@@ -181,7 +181,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[10]" = "true"
 			register "PcieClkSrcUsage[1]" = "10"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[10]" = "1"
+			register "PcieRpSlotImplemented[10]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pmc hidden

src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb

@@ -124,7 +124,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[2]" = "true"
 			register "PcieClkSrcUsage[1]" = "2"
 			register "PcieClkSrcClkReq[1]" = "1"
-			register "PcieRpSlotImplemented[2]" = "1"
+			register "PcieRpSlotImplemented[2]" = "true"
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
 		end
 		device ref pcie_rp6 on
@@ -139,7 +139,7 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[8]" = "true"
 			register "PcieClkSrcUsage[0]" = "8"
 			register "PcieClkSrcClkReq[0]" = "0"
-			register "PcieRpSlotImplemented[8]" = "1"
+			register "PcieRpSlotImplemented[8]" = "true"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN#
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly)

src/soc/intel/alderlake/fsp_params.c

@@ -927,7 +927,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
 		/* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */
 		if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
-			s_cfg->PcieRpSlotImplemented[i] = 0;
+			s_cfg->PcieRpSlotImplemented[i] = false;
 		s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
 		configure_pch_rp_power_management(s_cfg, rp_cfg, i);
 	}

src/soc/intel/tigerlake/chip.h

@@ -295,7 +295,7 @@ struct soc_intel_tigerlake_config {
 	/* PCIe Root Ports */
 	uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
 	/* Implemented as slot or built-in? */
-	uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
+	bool PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
 	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */