coreboot/src/soc/intel
Sean Rhodes 24ea6937f2 soc/intel/apollolake: Add the Kconfig options for IFWI Boot Profile
The Boot Profile for use with the IFWI Boot Flow. The selected profile
should be equal to or higher than the one configured in IFWI.

No Profile
  Since its inception, coreboot has ignored the Boot Flow designed by
  Intel; this only uses an IBB and OBB. Neither are measured or verified
  and mapped without assistance.

Legacy
  Profile 0 is for platforms that do not wish to enable Boot Guard boot
  block verification or measurement enforcement.

Verified
  Profile 1 is strict Verification enforcement. It prevents unverified
  BIOS components from running.

Verified and Measured
  Boot Guard Profile 2 is strict Verification and Measurement
  enforcement; this prevents unverified BIOS components from running.
  Upon manufacturing completion, this value is burned into an FPF
  and is permanent. This setting is only configurable when OEM signing
  is enabled.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I83d2fd134e1a893766f625fe2e2ddd81d48f9f8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66103
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-07-08 16:19:08 +00:00
..
alderlake soc/intel/alderlake: Enable USB3 HSIO related parameters for USB3 GEN2 support 2025-07-03 16:57:21 +00:00
apollolake soc/intel/apollolake: Add the Kconfig options for IFWI Boot Profile 2025-07-08 16:19:08 +00:00
baytrail soc/intel/baytrail: Add microcode for '06-37-08' SOCs 2025-02-03 18:59:45 +00:00
braswell tree: Handle NULL pointer returned by smm_get_save_state() 2025-01-20 03:26:26 +00:00
broadwell soc/intel/broadwell: Add CFR objects for existing options 2025-04-25 14:24:27 +00:00
cannonlake soc/intel: Move CNVI sideband definitions to SoC-specific files 2025-06-16 10:37:49 +00:00
common soc/intel/common/block/memory: Provide a way to use SPD data from memory 2025-07-07 14:32:11 +00:00
denverton_ns tree: remove duplicated includes 2025-04-20 05:13:57 +00:00
elkhartlake soc/intel/elkhartlake: Hook up S0ix setting to option API 2025-05-08 12:27:06 +00:00
jasperlake soc/intel: Move CNVI sideband definitions to SoC-specific files 2025-06-16 10:37:49 +00:00
meteorlake soc/intel: Add Arrow Lake-S/HX IDs 2025-07-03 16:57:15 +00:00
pantherlake soc/intel/ptl: Add Wildcat Lake CPU ID to platform reporting 2025-07-04 13:17:25 +00:00
skylake soc/intel/skylake: Expand USB OC pins enum to OC7 2025-06-24 04:25:53 +00:00
snowridge soc/intel/common/block: Add const qualifier for input of pirq ops 2024-12-09 13:55:53 +00:00
tigerlake tree: Use boolean for PcieRpSlotImplemented[] 2025-07-02 02:14:22 +00:00
xeon_sp Revert "soc/intel/xeon_sp/uncore.c: mark TSEG/SMM region as reserved" 2025-06-26 14:29:19 +00:00
Makefile.mk soc/intel: Rename Makefiles from .inc to .mk 2024-01-24 10:02:22 +00:00