soc/intel/pantherlake: Add new MCH ID for Wildcat Lake

This commit introduces a new MCH device ID to support the Wildcat
Lake SoC. It updates the PCI device ID list and platform reporting
logic to accommodate this new ID.

Key changes:
 - Add PCI_DID_INTEL_WCL_ID_3 (0xfd02) to the list of recognized
   device IDs.
 - Update system agent operations to include the new MCH ID.
 - Enhance platform reporting to recognize the new MCH ID.

References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I464fb147f0d3df214ca64b1321eebab08505d7bc
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88248
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Appukuttan V K 2025-06-30 16:47:40 +05:30 committed by Matt DeVillier
commit 9f73b04074
3 changed files with 3 additions and 0 deletions

View file

@ -4686,6 +4686,7 @@
#define PCI_DID_INTEL_SNR_ID 0x09a2
#define PCI_DID_INTEL_WCL_ID_1 0xfd00
#define PCI_DID_INTEL_WCL_ID_2 0xfd01
#define PCI_DID_INTEL_WCL_ID_3 0xfd02
/* Intel SMBUS device Ids */
#define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22

View file

@ -427,6 +427,7 @@ struct device_operations systemagent_ops = {
static const unsigned short systemagent_ids[] = {
PCI_DID_INTEL_WCL_ID_1,
PCI_DID_INTEL_WCL_ID_2,
PCI_DID_INTEL_WCL_ID_3,
PCI_DID_INTEL_PTL_U_ID_1,
PCI_DID_INTEL_PTL_U_ID_2,
PCI_DID_INTEL_PTL_U_ID_3,

View file

@ -42,6 +42,7 @@ static struct {
{ PCI_DID_INTEL_PTL_H_ID_8, "Pantherlake H" },
{ PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" },
{ PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" },
{ PCI_DID_INTEL_WCL_ID_3, "Wildcatlake" },
};
static struct {