soc/intel: Add Arrow Lake-S/HX IDs

Change-Id: I7a0a56cf80f053b4bb0c8acb9038c1e46dca5d2e
Ref: Intel Arrow Lake-S/HX EDS, Volume 1 (#729037, rev 2.01)
Ref: Intel 800 Series Chipset Family PCH EDS, Volume 1 (#728144, rev 1.52)
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87454
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/drivers/intel/ish/ish.c

@@ -91,6 +91,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_ISHB,
 	PCI_DID_INTEL_MTL_ISHB,
 	PCI_DID_INTEL_ARL_ISHB,
+	PCI_DID_INTEL_ARP_S_ISHB,
 	PCI_DID_INTEL_CNL_ISHB,
 	PCI_DID_INTEL_CML_ISHB,
 	PCI_DID_INTEL_TGL_ISHB,

src/include/device/pci_ids.h

@@ -2183,6 +2183,7 @@
 #define PCI_DID_INTEL_TGL_H_ISHB	0x43fc
 #define PCI_DID_INTEL_MTL_ISHB		0x7e45
 #define PCI_DID_INTEL_ARL_ISHB		0x7745
+#define PCI_DID_INTEL_ARP_S_ISHB	0x7f78
 #define PCI_DID_INTEL_ADL_N_ISHB	0x54fc
 #define PCI_DID_INTEL_ADL_P_ISHB	0x51fc
 #define PCI_DID_INTEL_LNL_ISHB		0xa845
@@ -3146,6 +3147,70 @@
 #define PCI_DID_INTEL_ARL_H_ESPI_0			0x7202
 #define PCI_DID_INTEL_ARL_H_ESPI_1			0x7702
 #define PCI_DID_INTEL_ARL_U_ESPI_0			0x7203
+#define PCI_DID_INTEL_ARL_S_ESPI_0			0xae00
+#define PCI_DID_INTEL_ARL_S_ESPI_1			0xae01
+#define PCI_DID_INTEL_ARL_S_ESPI_2			0xae02
+#define PCI_DID_INTEL_ARL_S_ESPI_3			0xae03
+#define PCI_DID_INTEL_ARL_S_ESPI_4			0xae04
+#define PCI_DID_INTEL_ARL_S_ESPI_5			0xae05
+#define PCI_DID_INTEL_ARL_S_ESPI_6			0xae06
+#define PCI_DID_INTEL_ARL_S_ESPI_7			0xae07
+#define PCI_DID_INTEL_ARL_S_ESPI_8			0xae08
+#define PCI_DID_INTEL_ARL_S_ESPI_9			0xae09
+#define PCI_DID_INTEL_ARL_S_ESPI_10			0xae0a
+#define PCI_DID_INTEL_ARL_S_ESPI_11			0xae0b
+#define PCI_DID_INTEL_ARL_S_ESPI_12			0xae0c
+#define PCI_DID_INTEL_ARL_S_ESPI_13			0xae0d
+#define PCI_DID_INTEL_ARL_S_ESPI_14			0xae0e
+#define PCI_DID_INTEL_ARL_S_ESPI_15			0xae0f
+#define PCI_DID_INTEL_ARL_S_ESPI_16			0xae10
+#define PCI_DID_INTEL_ARL_S_ESPI_17			0xae11
+#define PCI_DID_INTEL_ARL_S_ESPI_18			0xae12
+#define PCI_DID_INTEL_ARL_S_ESPI_19			0xae13
+#define PCI_DID_INTEL_ARL_S_ESPI_20			0xae14
+#define PCI_DID_INTEL_ARL_S_ESPI_21			0xae15
+#define PCI_DID_INTEL_ARL_S_ESPI_22			0xae16
+#define PCI_DID_INTEL_ARL_S_ESPI_23			0xae17
+#define PCI_DID_INTEL_ARL_S_ESPI_24			0xae18
+#define PCI_DID_INTEL_ARL_S_ESPI_25			0xae19
+#define PCI_DID_INTEL_ARL_S_ESPI_26			0xae1a
+#define PCI_DID_INTEL_ARL_S_ESPI_27			0xae1b
+#define PCI_DID_INTEL_ARL_S_ESPI_28			0xae1c
+#define PCI_DID_INTEL_ARL_S_ESPI_29			0xae1d
+#define PCI_DID_INTEL_ARL_S_ESPI_30			0xae1e
+#define PCI_DID_INTEL_ARL_S_ESPI_31			0xae1f
+#define PCI_DID_INTEL_ARP_S_ESPI_0			0x7f00
+#define PCI_DID_INTEL_ARP_S_ESPI_1			0x7f01
+#define PCI_DID_INTEL_ARP_S_ESPI_2			0x7f02
+#define PCI_DID_INTEL_ARP_S_ESPI_3			0x7f03
+#define PCI_DID_INTEL_ARP_S_ESPI_4			0x7f04
+#define PCI_DID_INTEL_ARP_S_ESPI_5			0x7f05
+#define PCI_DID_INTEL_ARP_S_ESPI_6			0x7f06
+#define PCI_DID_INTEL_ARP_S_ESPI_7			0x7f07
+#define PCI_DID_INTEL_ARP_S_ESPI_8			0x7f08
+#define PCI_DID_INTEL_ARP_S_ESPI_9			0x7f09
+#define PCI_DID_INTEL_ARP_S_ESPI_10			0x7f0a
+#define PCI_DID_INTEL_ARP_S_ESPI_11			0x7f0b
+#define PCI_DID_INTEL_ARP_S_ESPI_12			0x7f0c
+#define PCI_DID_INTEL_ARP_S_ESPI_13			0x7f0d
+#define PCI_DID_INTEL_ARP_S_ESPI_14			0x7f0e
+#define PCI_DID_INTEL_ARP_S_ESPI_15			0x7f0f
+#define PCI_DID_INTEL_ARP_S_ESPI_16			0x7f10
+#define PCI_DID_INTEL_ARP_S_ESPI_17			0x7f11
+#define PCI_DID_INTEL_ARP_S_ESPI_18			0x7f12
+#define PCI_DID_INTEL_ARP_S_ESPI_19			0x7f13
+#define PCI_DID_INTEL_ARP_S_ESPI_20			0x7f14
+#define PCI_DID_INTEL_ARP_S_ESPI_21			0x7f15
+#define PCI_DID_INTEL_ARP_S_ESPI_22			0x7f16
+#define PCI_DID_INTEL_ARP_S_ESPI_23			0x7f17
+#define PCI_DID_INTEL_ARP_S_ESPI_24			0x7f18
+#define PCI_DID_INTEL_ARP_S_ESPI_25			0x7f19
+#define PCI_DID_INTEL_ARP_S_ESPI_26			0x7f1a
+#define PCI_DID_INTEL_ARP_S_ESPI_27			0x7f1b
+#define PCI_DID_INTEL_ARP_S_ESPI_28			0x7f1c
+#define PCI_DID_INTEL_ARP_S_ESPI_29			0x7f1d
+#define PCI_DID_INTEL_ARP_S_ESPI_30			0x7f1e
+#define PCI_DID_INTEL_ARP_S_ESPI_31			0x7f1f
 #define PCI_DID_INTEL_RPP_P_ESPI_0			0x5180
 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1		0x5181
 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2		0x5182
@@ -3650,6 +3715,34 @@
 #define PCI_DID_INTEL_ARL_SOC_PCIE_RP7			0x773e
 #define PCI_DID_INTEL_ARL_SOC_PCIE_RP8			0x773f
 #define PCI_DID_INTEL_ARL_SOC_PCIE_RP9			0x774d
+#define PCI_DID_INTEL_ARL_S_PCIE_RP13			0xae4d
+#define PCI_DID_INTEL_ARL_S_PCIE_RP14			0xae4e
+#define PCI_DID_INTEL_ARL_S_PCIE_RP15			0xae4f
+
+#define PCI_DID_INTEL_ARP_S_PCIE_RP1			0x7f38
+#define PCI_DID_INTEL_ARP_S_PCIE_RP2			0x7f39
+#define PCI_DID_INTEL_ARP_S_PCIE_RP3			0x7f3a
+#define PCI_DID_INTEL_ARP_S_PCIE_RP4			0x7f3b
+#define PCI_DID_INTEL_ARP_S_PCIE_RP5			0x7f3c
+#define PCI_DID_INTEL_ARP_S_PCIE_RP6			0x7f3d
+#define PCI_DID_INTEL_ARP_S_PCIE_RP7			0x7f3e
+#define PCI_DID_INTEL_ARP_S_PCIE_RP8			0x7f3f
+#define PCI_DID_INTEL_ARP_S_PCIE_RP9			0x7f30
+#define PCI_DID_INTEL_ARP_S_PCIE_RP10			0x7f31
+#define PCI_DID_INTEL_ARP_S_PCIE_RP11			0x7f32
+#define PCI_DID_INTEL_ARP_S_PCIE_RP12			0x7f33
+#define PCI_DID_INTEL_ARP_S_PCIE_RP13			0x7f34
+#define PCI_DID_INTEL_ARP_S_PCIE_RP14			0x7f35
+#define PCI_DID_INTEL_ARP_S_PCIE_RP15			0x7f36
+#define PCI_DID_INTEL_ARP_S_PCIE_RP16			0x7f37
+#define PCI_DID_INTEL_ARP_S_PCIE_RP17			0x7f40
+#define PCI_DID_INTEL_ARP_S_PCIE_RP18			0x7f41
+#define PCI_DID_INTEL_ARP_S_PCIE_RP19			0x7f42
+#define PCI_DID_INTEL_ARP_S_PCIE_RP20			0x7f43
+#define PCI_DID_INTEL_ARP_S_PCIE_RP21			0x7f44
+#define PCI_DID_INTEL_ARP_S_PCIE_RP22			0x7f45
+#define PCI_DID_INTEL_ARP_S_PCIE_RP23			0x7f46
+#define PCI_DID_INTEL_ARP_S_PCIE_RP24			0x7f47
 
 #define PCI_DID_INTEL_RPL_P_PCIE_RP1			0xa74d
 #define PCI_DID_INTEL_RPL_P_PCIE_RP2			0xa70d
@@ -3820,6 +3913,8 @@
 #define PCI_DID_INTEL_ADP_M_SATA_3		0x282a
 #define PCI_DID_INTEL_MTL_SATA			0x7e63
 #define PCI_DID_INTEL_ARL_SATA			0x7763
+#define PCI_DID_INTEL_ARP_S_SATA_1		0x7f62
+#define PCI_DID_INTEL_ARP_S_SATA_2		0x7f66
 #define PCI_DID_INTEL_RPP_P_SATA_1		0x51d3
 #define PCI_DID_INTEL_RPP_P_SATA_2		0x51d7
 #define PCI_DID_INTEL_RPP_S_SATA		0x7a62
@@ -3850,6 +3945,8 @@
 #define PCI_DID_INTEL_MTL_IOE_M_PMC		0x7ebe
 #define PCI_DID_INTEL_MTL_IOE_P_PMC		0x7ece
 #define PCI_DID_INTEL_ARL_SOC_PMC		0x7721
+#define PCI_DID_INTEL_ARL_IOE_S_PMC		0xae21
+#define PCI_DID_INTEL_ARP_S_PMC			0x7f21
 #define PCI_DID_INTEL_RPP_P_PMC			0x51a1
 #define PCI_DID_INTEL_RPP_S_PMC			0x7a21
 #define PCI_DID_INTEL_LNL_PMC			0xa821
@@ -3987,6 +4084,13 @@
 #define PCI_DID_INTEL_ARL_I2C4			0x7750
 #define PCI_DID_INTEL_ARL_I2C5			0x7751
 
+#define PCI_DID_INTEL_ARP_S_I2C0		0x7f4c
+#define PCI_DID_INTEL_ARP_S_I2C1		0x7f4d
+#define PCI_DID_INTEL_ARP_S_I2C2		0x7f4e
+#define PCI_DID_INTEL_ARP_S_I2C3		0x7f4f
+#define PCI_DID_INTEL_ARP_S_I2C4		0x7f7a
+#define PCI_DID_INTEL_ARP_S_I2C5		0x7f7b
+
 #define PCI_DID_INTEL_LNL_I2C0			0xa878
 #define PCI_DID_INTEL_LNL_I2C1			0xa879
 #define PCI_DID_INTEL_LNL_I2C2			0xa87a
@@ -4097,6 +4201,11 @@
 #define PCI_DID_INTEL_ARL_UART1			0x7726
 #define PCI_DID_INTEL_ARL_UART2			0x7752
 
+#define PCI_DID_INTEL_ARP_S_UART0		0x7f28
+#define PCI_DID_INTEL_ARP_S_UART1		0x7f29
+#define PCI_DID_INTEL_ARP_S_UART2		0x7f5c
+#define PCI_DID_INTEL_ARP_S_UART3		0x7f5d
+
 #define PCI_DID_INTEL_LNL_UART0			0xa825
 #define PCI_DID_INTEL_LNL_UART1			0xa826
 #define PCI_DID_INTEL_LNL_UART2			0xa852
@@ -4211,6 +4320,13 @@
 #define PCI_DID_INTEL_ARL_GSPI1			0x7730
 #define PCI_DID_INTEL_ARL_GSPI2			0x7746
 
+#define PCI_DID_INTEL_ARL_S_HWSEQ_SPI		0xae23
+#define PCI_DID_INTEL_ARP_S_HWSEQ_SPI		0x7f24
+#define PCI_DID_INTEL_ARP_S_GSPI0		0x7f2a
+#define PCI_DID_INTEL_ARP_S_GSPI1		0x7f2b
+#define PCI_DID_INTEL_ARP_S_GSPI2		0x7f5e
+#define PCI_DID_INTEL_ARP_S_GSPI3		0x7f5f
+
 #define PCI_DID_INTEL_LNL_HWSEQ_SPI		0xa823
 #define PCI_DID_INTEL_LNL_GSPI0			0xa827
 #define PCI_DID_INTEL_LNL_GSPI1			0xa830
@@ -4597,6 +4713,8 @@
 #define PCI_DID_INTEL_ADP_M_N_SMBUS			0x54a3
 #define PCI_DID_INTEL_MTL_SMBUS				0x7e22
 #define PCI_DID_INTEL_ARL_SMBUS				0x7722
+#define PCI_DID_INTEL_ARL_S_SMBUS			0xae22
+#define PCI_DID_INTEL_ARP_S_SMBUS			0x7f22
 #define PCI_DID_INTEL_RPP_P_SMBUS			0x51a3
 #define PCI_DID_INTEL_RPP_S_SMBUS			0x7a23
 #define PCI_DID_INTEL_LNL_SMBUS				0xa822
@@ -4642,6 +4760,7 @@
 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI		0x7ec0
 #define PCI_DID_INTEL_ARL_XHCI			0x777d
+#define PCI_DID_INTEL_ARP_S_XHCI		0x7f6e
 #define PCI_DID_INTEL_RPP_P_TCSS_XHCI		0xa71e
 #define PCI_DID_INTEL_RPP_S_XHCI		0x7a60
 #define PCI_DID_INTEL_LNL_XHCI			0xa87d
@@ -4678,6 +4797,8 @@
 #define PCI_DID_INTEL_MTL_IOE_M_P2SB		0x7eb8
 #define PCI_DID_INTEL_MTL_IOE_P_P2SB		0x7ec8
 #define PCI_DID_INTEL_ARL_SOC_P2SB		0x7720
+#define PCI_DID_INTEL_ARL_IOE_S_P2SB		0xae20
+#define PCI_DID_INTEL_ARP_S_P2SB		0x7f20
 #define PCI_DID_INTEL_RPP_P_P2SB		0x51a0
 #define PCI_DID_INTEL_RPP_S_P2SB		0x7a20
 #define PCI_DID_INTEL_LNL_P2SB			0xa820
@@ -4704,6 +4825,8 @@
 #define PCI_DID_INTEL_MTL_IOE_M_SRAM		0x7ebf
 #define PCI_DID_INTEL_MTL_IOE_P_SRAM		0x7ecf
 #define PCI_DID_INTEL_ARL_SOC_SRAM		0x777f
+#define PCI_DID_INTEL_ARL_SOC_S_SRAM		0xae7f
+#define PCI_DID_INTEL_ARP_S_SRAM		0x7f27
 #define PCI_DID_INTEL_LNL_SRAM			0xa87f
 #define PCI_DID_INTEL_PTL_H_SRAM		0xe47f
 #define PCI_DID_INTEL_PTL_U_H_SRAM		0xe37f
@@ -4767,6 +4890,8 @@
 
 #define PCI_DID_INTEL_ARL_AUDIO		0x7728
 
+#define PCI_DID_INTEL_ARP_S_AUDIO		0x7f50
+
 #define PCI_DID_INTEL_LNL_AUDIO_1		0xa828
 #define PCI_DID_INTEL_LNL_AUDIO_2		0xa829
 #define PCI_DID_INTEL_LNL_AUDIO_3		0xa82a
@@ -4847,6 +4972,13 @@
 #define PCI_DID_INTEL_RPP_S_CSE3		0x7a6d
 #define PCI_DID_INTEL_MTL_CSE0			0x7e70
 #define PCI_DID_INTEL_ARL_CSE0			0x7770
+#define PCI_DID_INTEL_ARL_S_CSE0		0xae70
+#define PCI_DID_INTEL_ARL_S_CSE1		0xae71
+#define PCI_DID_INTEL_ARL_S_CSE2		0xae74
+#define PCI_DID_INTEL_ARP_S_CSE0		0x7f68
+#define PCI_DID_INTEL_ARP_S_CSE1		0x7f69
+#define PCI_DID_INTEL_ARP_S_CSE2		0x7f6c
+#define PCI_DID_INTEL_ARP_S_CSE3		0x7f6d
 #define PCI_DID_INTEL_LNL_CSE0			0xa870
 #define PCI_DID_INTEL_PTL_H_CSE0		0xe470
 #define PCI_DID_INTEL_PTL_U_H_CSE0		0xe370
@@ -4876,6 +5008,7 @@
 #define PCI_DID_INTEL_MTL_M_TCSS_XDCI		0x7eb1
 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
 #define PCI_DID_INTEL_ARL_XDCI			0x777e
+#define PCI_DID_INTEL_ARP_S_XDCI			0x7f6f
 #define PCI_DID_INTEL_PTL_H_XDCI		0xe47e
 #define PCI_DID_INTEL_PTL_U_H_XDCI		0xe37e
 #define PCI_DID_INTEL_WCL_XDCI		0x4d7e
@@ -4989,6 +5122,7 @@
 #define PCI_DID_INTEL_JSL_DTT			0x4E03
 #define PCI_DID_INTEL_ADL_DTT			0x461d
 #define PCI_DID_INTEL_MTL_DTT			0x7d03
+#define PCI_DID_INTEL_ARL_S_DTT			0xad03
 #define PCI_DID_INTEL_RPL_DTT			0xa71d
 #define PCI_DID_INTEL_PTL_DTT			0xb01d
 #define PCI_DID_INTEL_WCL_DTT			0xfd1d
@@ -5035,6 +5169,7 @@
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2		0x7e42
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3		0x7e43
 #define PCI_DID_INTEL_ARL_CNVI_WIFI		0x7740
+#define PCI_DID_INTEL_ARP_S_CNVI_WIFI		0x7f70
 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0		0x7a70
 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1		0x7a71
 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2		0x7a72
@@ -5079,6 +5214,7 @@
 #define PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM		0x54ef
 #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM		0xa0ef
 #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM			0x7d0d
+#define PCI_DID_INTEL_ARL_S_CRASHLOG_SRAM		0xad0d
 #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d
 #define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM		0x7a27
 #define PCI_DID_INTEL_PTL_PUNIT_CRASHLOG_SRAM		0xb07d
@@ -5087,6 +5223,8 @@
 /* Intel Trace Hub */
 #define PCI_DID_INTEL_MTL_TRACEHUB			0x7e24
 #define PCI_DID_INTEL_ARL_TRACEHUB			0x7724
+#define PCI_DID_INTEL_ARL_S_TRACEHUB			0xae24
+#define PCI_DID_INTEL_ARP_S_TRACEHUB			0x7f26
 #define PCI_DID_INTEL_RPL_TRACEHUB			0xa76f
 #define PCI_DID_INTEL_PTL_H_TRACEHUB			0xe424
 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB			0xe324
@@ -5118,6 +5256,10 @@
 #define PCI_DID_INTEL_ARL_THC0_2	0x7749
 #define PCI_DID_INTEL_ARL_THC1_1	0x774a
 #define PCI_DID_INTEL_ARL_THC1_2	0x774b
+#define PCI_DID_INTEL_ARP_S_THC0_1	0x7f58
+#define PCI_DID_INTEL_ARP_S_THC0_2	0x7f59
+#define PCI_DID_INTEL_ARP_S_THC1_1	0x7f5a
+#define PCI_DID_INTEL_ARP_S_THC1_2	0x7f5b
 
 #define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291

src/soc/intel/common/block/cnvi/cnvi.c

@@ -489,6 +489,7 @@ static const unsigned short wifi_pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_CNVI_WIFI_2,
 	PCI_DID_INTEL_MTL_CNVI_WIFI_3,
 	PCI_DID_INTEL_ARL_CNVI_WIFI,
+	PCI_DID_INTEL_ARP_S_CNVI_WIFI,
 	PCI_DID_INTEL_CML_LP_CNVI_WIFI,
 	PCI_DID_INTEL_CML_H_CNVI_WIFI,
 	PCI_DID_INTEL_CNL_LP_CNVI_WIFI,

src/soc/intel/common/block/cse/cse.c

@@ -1533,6 +1533,13 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_CSE0,
 	PCI_DID_INTEL_MTL_CSE0,
 	PCI_DID_INTEL_ARL_CSE0,
+	PCI_DID_INTEL_ARL_S_CSE0,
+	PCI_DID_INTEL_ARL_S_CSE1,
+	PCI_DID_INTEL_ARL_S_CSE2,
+	PCI_DID_INTEL_ARP_S_CSE0,
+	PCI_DID_INTEL_ARP_S_CSE1,
+	PCI_DID_INTEL_ARP_S_CSE2,
+	PCI_DID_INTEL_ARP_S_CSE3,
 	PCI_DID_INTEL_APL_CSE0,
 	PCI_DID_INTEL_GLK_CSE0,
 	PCI_DID_INTEL_CNL_CSE0,

src/soc/intel/common/block/dsp/dsp.c

@@ -54,6 +54,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_AUDIO_7,
 	PCI_DID_INTEL_MTL_AUDIO_8,
 	PCI_DID_INTEL_ARL_AUDIO,
+	PCI_DID_INTEL_ARP_S_AUDIO,
 	PCI_DID_INTEL_RPP_P_AUDIO,
 	PCI_DID_INTEL_RPP_S_AUDIO_1,
 	PCI_DID_INTEL_RPP_S_AUDIO_2,

src/soc/intel/common/block/dtt/dtt.c

@@ -12,6 +12,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_DTT,
 	PCI_DID_INTEL_RPL_DTT,
 	PCI_DID_INTEL_MTL_DTT,
+	PCI_DID_INTEL_ARL_S_DTT,
 	PCI_DID_INTEL_CML_DTT,
 	PCI_DID_INTEL_TGL_DTT,
 	PCI_DID_INTEL_JSL_DTT,

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -578,6 +578,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MCC_SPI0,
 	PCI_DID_INTEL_MTL_HWSEQ_SPI,
 	PCI_DID_INTEL_ARL_HWSEQ_SPI,
+	PCI_DID_INTEL_ARL_S_HWSEQ_SPI,
+	PCI_DID_INTEL_ARP_S_HWSEQ_SPI,
 	PCI_DID_INTEL_RPP_S_HWSEQ_SPI,
 	PCI_DID_INTEL_SPR_HWSEQ_SPI,
 	PCI_DID_INTEL_TGP_SPI0,

src/soc/intel/common/block/hda/hda.c

@@ -70,6 +70,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_AUDIO_7,
 	PCI_DID_INTEL_MTL_AUDIO_8,
 	PCI_DID_INTEL_ARL_AUDIO,
+	PCI_DID_INTEL_ARP_S_AUDIO,
 	PCI_DID_INTEL_RPP_P_AUDIO,
 	PCI_DID_INTEL_RPP_S_AUDIO_1,
 	PCI_DID_INTEL_RPP_S_AUDIO_2,

src/soc/intel/common/block/i2c/i2c.c

@@ -210,6 +210,12 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ARL_I2C3,
 	PCI_DID_INTEL_ARL_I2C4,
 	PCI_DID_INTEL_ARL_I2C5,
+	PCI_DID_INTEL_ARP_S_I2C0,
+	PCI_DID_INTEL_ARP_S_I2C1,
+	PCI_DID_INTEL_ARP_S_I2C2,
+	PCI_DID_INTEL_ARP_S_I2C3,
+	PCI_DID_INTEL_ARP_S_I2C4,
+	PCI_DID_INTEL_ARP_S_I2C5,
 	PCI_DID_INTEL_APL_I2C0,
 	PCI_DID_INTEL_APL_I2C1,
 	PCI_DID_INTEL_APL_I2C2,

src/soc/intel/common/block/lpc/lpc.c

@@ -266,6 +266,70 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ARL_H_ESPI_0,
 	PCI_DID_INTEL_ARL_H_ESPI_1,
 	PCI_DID_INTEL_ARL_U_ESPI_0,
+	PCI_DID_INTEL_ARL_S_ESPI_0,
+	PCI_DID_INTEL_ARL_S_ESPI_1,
+	PCI_DID_INTEL_ARL_S_ESPI_2,
+	PCI_DID_INTEL_ARL_S_ESPI_3,
+	PCI_DID_INTEL_ARL_S_ESPI_4,
+	PCI_DID_INTEL_ARL_S_ESPI_5,
+	PCI_DID_INTEL_ARL_S_ESPI_6,
+	PCI_DID_INTEL_ARL_S_ESPI_7,
+	PCI_DID_INTEL_ARL_S_ESPI_8,
+	PCI_DID_INTEL_ARL_S_ESPI_9,
+	PCI_DID_INTEL_ARL_S_ESPI_10,
+	PCI_DID_INTEL_ARL_S_ESPI_11,
+	PCI_DID_INTEL_ARL_S_ESPI_12,
+	PCI_DID_INTEL_ARL_S_ESPI_13,
+	PCI_DID_INTEL_ARL_S_ESPI_14,
+	PCI_DID_INTEL_ARL_S_ESPI_15,
+	PCI_DID_INTEL_ARL_S_ESPI_16,
+	PCI_DID_INTEL_ARL_S_ESPI_17,
+	PCI_DID_INTEL_ARL_S_ESPI_18,
+	PCI_DID_INTEL_ARL_S_ESPI_19,
+	PCI_DID_INTEL_ARL_S_ESPI_20,
+	PCI_DID_INTEL_ARL_S_ESPI_21,
+	PCI_DID_INTEL_ARL_S_ESPI_22,
+	PCI_DID_INTEL_ARL_S_ESPI_23,
+	PCI_DID_INTEL_ARL_S_ESPI_24,
+	PCI_DID_INTEL_ARL_S_ESPI_25,
+	PCI_DID_INTEL_ARL_S_ESPI_26,
+	PCI_DID_INTEL_ARL_S_ESPI_27,
+	PCI_DID_INTEL_ARL_S_ESPI_28,
+	PCI_DID_INTEL_ARL_S_ESPI_29,
+	PCI_DID_INTEL_ARL_S_ESPI_30,
+	PCI_DID_INTEL_ARL_S_ESPI_31,
+	PCI_DID_INTEL_ARP_S_ESPI_0,
+	PCI_DID_INTEL_ARP_S_ESPI_1,
+	PCI_DID_INTEL_ARP_S_ESPI_2,
+	PCI_DID_INTEL_ARP_S_ESPI_3,
+	PCI_DID_INTEL_ARP_S_ESPI_4,
+	PCI_DID_INTEL_ARP_S_ESPI_5,
+	PCI_DID_INTEL_ARP_S_ESPI_6,
+	PCI_DID_INTEL_ARP_S_ESPI_7,
+	PCI_DID_INTEL_ARP_S_ESPI_8,
+	PCI_DID_INTEL_ARP_S_ESPI_9,
+	PCI_DID_INTEL_ARP_S_ESPI_10,
+	PCI_DID_INTEL_ARP_S_ESPI_11,
+	PCI_DID_INTEL_ARP_S_ESPI_12,
+	PCI_DID_INTEL_ARP_S_ESPI_13,
+	PCI_DID_INTEL_ARP_S_ESPI_14,
+	PCI_DID_INTEL_ARP_S_ESPI_15,
+	PCI_DID_INTEL_ARP_S_ESPI_16,
+	PCI_DID_INTEL_ARP_S_ESPI_17,
+	PCI_DID_INTEL_ARP_S_ESPI_18,
+	PCI_DID_INTEL_ARP_S_ESPI_19,
+	PCI_DID_INTEL_ARP_S_ESPI_20,
+	PCI_DID_INTEL_ARP_S_ESPI_21,
+	PCI_DID_INTEL_ARP_S_ESPI_22,
+	PCI_DID_INTEL_ARP_S_ESPI_23,
+	PCI_DID_INTEL_ARP_S_ESPI_24,
+	PCI_DID_INTEL_ARP_S_ESPI_25,
+	PCI_DID_INTEL_ARP_S_ESPI_26,
+	PCI_DID_INTEL_ARP_S_ESPI_27,
+	PCI_DID_INTEL_ARP_S_ESPI_28,
+	PCI_DID_INTEL_ARP_S_ESPI_29,
+	PCI_DID_INTEL_ARP_S_ESPI_30,
+	PCI_DID_INTEL_ARP_S_ESPI_31,
 	PCI_DID_INTEL_RPP_P_ESPI_0,
 	PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1,
 	PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2,

src/soc/intel/common/block/p2sb/p2sb.c

@@ -143,6 +143,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_P2SB,
 	PCI_DID_INTEL_MTL_SOC_P2SB,
 	PCI_DID_INTEL_ARL_SOC_P2SB,
+	PCI_DID_INTEL_ARL_IOE_S_P2SB,
+	PCI_DID_INTEL_ARP_S_P2SB,
 	PCI_DID_INTEL_RPP_P_P2SB,
 	PCI_DID_INTEL_APL_P2SB,
 	PCI_DID_INTEL_GLK_P2SB,

src/soc/intel/common/block/pcie/pcie.c

@@ -128,6 +128,33 @@ static const unsigned short pcie_device_ids[] = {
 	PCI_DID_INTEL_ARL_SOC_PCIE_RP7,
 	PCI_DID_INTEL_ARL_SOC_PCIE_RP8,
 	PCI_DID_INTEL_ARL_SOC_PCIE_RP9,
+	PCI_DID_INTEL_ARL_S_PCIE_RP13,
+	PCI_DID_INTEL_ARL_S_PCIE_RP14,
+	PCI_DID_INTEL_ARL_S_PCIE_RP15,
+	PCI_DID_INTEL_ARP_S_PCIE_RP1,
+	PCI_DID_INTEL_ARP_S_PCIE_RP2,
+	PCI_DID_INTEL_ARP_S_PCIE_RP3,
+	PCI_DID_INTEL_ARP_S_PCIE_RP4,
+	PCI_DID_INTEL_ARP_S_PCIE_RP5,
+	PCI_DID_INTEL_ARP_S_PCIE_RP6,
+	PCI_DID_INTEL_ARP_S_PCIE_RP7,
+	PCI_DID_INTEL_ARP_S_PCIE_RP8,
+	PCI_DID_INTEL_ARP_S_PCIE_RP9,
+	PCI_DID_INTEL_ARP_S_PCIE_RP10,
+	PCI_DID_INTEL_ARP_S_PCIE_RP11,
+	PCI_DID_INTEL_ARP_S_PCIE_RP12,
+	PCI_DID_INTEL_ARP_S_PCIE_RP13,
+	PCI_DID_INTEL_ARP_S_PCIE_RP14,
+	PCI_DID_INTEL_ARP_S_PCIE_RP15,
+	PCI_DID_INTEL_ARP_S_PCIE_RP16,
+	PCI_DID_INTEL_ARP_S_PCIE_RP17,
+	PCI_DID_INTEL_ARP_S_PCIE_RP18,
+	PCI_DID_INTEL_ARP_S_PCIE_RP19,
+	PCI_DID_INTEL_ARP_S_PCIE_RP20,
+	PCI_DID_INTEL_ARP_S_PCIE_RP21,
+	PCI_DID_INTEL_ARP_S_PCIE_RP22,
+	PCI_DID_INTEL_ARP_S_PCIE_RP23,
+	PCI_DID_INTEL_ARP_S_PCIE_RP24,
 	PCI_DID_INTEL_LWB_PCIE_RP1,
 	PCI_DID_INTEL_LWB_PCIE_RP2,
 	PCI_DID_INTEL_LWB_PCIE_RP3,

src/soc/intel/common/block/pmc/pmc.c

@@ -119,6 +119,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_IOE_M_PMC,
 	PCI_DID_INTEL_MTL_IOE_P_PMC,
 	PCI_DID_INTEL_ARL_SOC_PMC,
+	PCI_DID_INTEL_ARL_IOE_S_PMC,
+	PCI_DID_INTEL_ARP_S_PMC,
 	PCI_DID_INTEL_RPP_P_PMC,
 	PCI_DID_INTEL_DNV_PMC,
 	PCI_DID_INTEL_LWB_PMC,

src/soc/intel/common/block/sata/sata.c

@@ -37,6 +37,8 @@ struct device_operations sata_ops = {
 static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_SATA,
 	PCI_DID_INTEL_ARL_SATA,
+	PCI_DID_INTEL_ARP_S_SATA_1,
+	PCI_DID_INTEL_ARP_S_SATA_2,
 	PCI_DID_INTEL_RPP_P_SATA_1,
 	PCI_DID_INTEL_RPP_P_SATA_2,
 	PCI_DID_INTEL_RPP_S_SATA,

src/soc/intel/common/block/smbus/smbus.c

@@ -55,6 +55,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_SMBUS,
 	PCI_DID_INTEL_MTL_SMBUS,
 	PCI_DID_INTEL_ARL_SMBUS,
+	PCI_DID_INTEL_ARL_S_SMBUS,
+	PCI_DID_INTEL_ARP_S_SMBUS,
 	PCI_DID_INTEL_RPP_P_SMBUS,
 	PCI_DID_INTEL_RPP_S_SMBUS,
 	PCI_DID_INTEL_APL_SMBUS,

src/soc/intel/common/block/spi/spi.c

@@ -144,6 +144,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ARL_GSPI0,
 	PCI_DID_INTEL_ARL_GSPI1,
 	PCI_DID_INTEL_ARL_GSPI2,
+	PCI_DID_INTEL_ARP_S_GSPI0,
+	PCI_DID_INTEL_ARP_S_GSPI1,
+	PCI_DID_INTEL_ARP_S_GSPI2,
+	PCI_DID_INTEL_ARP_S_GSPI3,
 	PCI_DID_INTEL_APL_SPI0,
 	PCI_DID_INTEL_APL_SPI1,
 	PCI_DID_INTEL_APL_SPI2,

src/soc/intel/common/block/sram/sram.c

@@ -43,7 +43,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_MTL_IOE_M_SRAM,
 	PCI_DID_INTEL_MTL_IOE_P_SRAM,
 	PCI_DID_INTEL_MTL_CRASHLOG_SRAM,
+	PCI_DID_INTEL_ARL_S_CRASHLOG_SRAM,
 	PCI_DID_INTEL_ARL_SOC_SRAM,
+	PCI_DID_INTEL_ARL_SOC_S_SRAM,
+	PCI_DID_INTEL_ARP_S_SRAM,
 	PCI_DID_INTEL_APL_SRAM,
 	PCI_DID_INTEL_GLK_SRAM,
 	PCI_DID_INTEL_CMP_SRAM,

src/soc/intel/common/block/tracehub/tracehub.c

@@ -47,6 +47,8 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_U_H_TRACEHUB,
 	PCI_DID_INTEL_MTL_TRACEHUB,
 	PCI_DID_INTEL_ARL_TRACEHUB,
+	PCI_DID_INTEL_ARL_S_TRACEHUB,
+	PCI_DID_INTEL_ARP_S_TRACEHUB,
 	PCI_DID_INTEL_RPL_TRACEHUB,
 	0
 };

src/soc/intel/common/block/uart/uart.c

@@ -378,6 +378,10 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_ARL_UART0,
 	PCI_DID_INTEL_ARL_UART1,
 	PCI_DID_INTEL_ARL_UART2,
+	PCI_DID_INTEL_ARP_S_UART0,
+	PCI_DID_INTEL_ARP_S_UART1,
+	PCI_DID_INTEL_ARP_S_UART2,
+	PCI_DID_INTEL_ARP_S_UART3,
 	PCI_DID_INTEL_APL_UART0,
 	PCI_DID_INTEL_APL_UART1,
 	PCI_DID_INTEL_APL_UART2,

src/soc/intel/common/block/xdci/xdci.c

@@ -33,6 +33,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_PTL_U_H_XDCI,
 	PCI_DID_INTEL_MTL_XDCI,
 	PCI_DID_INTEL_ARL_XDCI,
+	PCI_DID_INTEL_ARP_S_XDCI,
 	PCI_DID_INTEL_APL_XDCI,
 	PCI_DID_INTEL_CNL_LP_XDCI,
 	PCI_DID_INTEL_GLK_XDCI,

src/soc/intel/common/block/xhci/xhci.c

@@ -137,6 +137,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_LNL_XHCI,
 	PCI_DID_INTEL_MTL_XHCI,
 	PCI_DID_INTEL_ARL_XHCI,
+	PCI_DID_INTEL_ARP_S_XHCI,
 	PCI_DID_INTEL_APL_XHCI,
 	PCI_DID_INTEL_CNL_LP_XHCI,
 	PCI_DID_INTEL_GLK_XHCI,

src/soc/intel/meteorlake/Makefile.mk

@@ -57,6 +57,7 @@ smm-y += smihandler.c
 smm-y += soc_info.c
 smm-y += uart.c
 smm-y += xhci.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/meteorlake
 CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include