soc/intel/meteorlake: Fix DDR5 channel mapping

This patch applies commit 0e7cf3d81d ("soc/intel/alderlake: Fix DDR5
channel mapping") to Meteor Lake.

DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Meteor
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.

To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.

Change-Id: I00cd1fba855a50422a68fa662df4ca8ed2c6458d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88636
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/meteorlake/meminit.c

@@ -38,18 +38,16 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 		.num_phys_channels = DDR5_CHANNELS,
 		.phys_to_mrc_map = {
 			[0] = 0,
-			[1] = 1,
-			[2] = 4,
-			[3] = 5,
+			[1] = 4,
 		},
 		.md_phy_masks = {
 			/*
-			 * Physical channels 0 and 1 are populated in case of
-			 * half-populated configurations.
+			 * Only channel 0 is populated in case of half-populated
+			 * configuration.
 			 */
-			.half_channel = BIT(0) | BIT(1),
-			/* In mixed topologies, channels 2 and 3 are always memory-down. */
-			.mixed_topo = BIT(2) | BIT(3),
+			.half_channel = BIT(0),
+			/* In mixed topologies, either channel 0 or 1 can be memory-down. */
+			.mixed_topo = BIT(0) | BIT(1),
 		},
 	},
 	[MEM_TYPE_LP5X] = {