device/dram: Rename 'USE_DDRx' config options

Rename config options 'USE_DDRx' to 'DRAM_SUPPORT_DDRx' to make them
less clunky, and in preparation to expand their use inside SoC code.

Change-Id: Ie6edd730c5cbad679a90fcf7989a942d9b2dd3d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/device/dram/Kconfig

@@ -1,31 +1,31 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config USE_DDR5
+config DRAM_SUPPORT_DDR5
 	bool
 	default n
 	help
-	  system supports DDR5 memory
+	  System supports DDR5 memory
 
-config USE_LPDDR4
+config DRAM_SUPPORT_LPDDR4
 	bool
 	default n
 	help
-	  system supports LPDDR4 memory
+	  System supports LPDDR4 memory
 
-config USE_DDR4
+config DRAM_SUPPORT_DDR4
 	bool
 	default n
 	help
-	  system supports DDR4 memory
+	  System supports DDR4 memory
 
-config USE_DDR3
+config DRAM_SUPPORT_DDR3
 	bool
 	default n
 	help
-	  system supports DDR3 memory
+	  System supports DDR3 memory
 
-config USE_DDR2
+config DRAM_SUPPORT_DDR2
 	bool
 	default n
 	help
-	  system supports DDR2 memory
+	  System supports DDR2 memory

src/device/dram/Makefile.mk

@@ -4,18 +4,18 @@ romstage-y += ddr_common.c
 ramstage-y += ddr_common.c
 ramstage-y += spd.c
 
-romstage-$(CONFIG_USE_DDR5) += ddr5.c
-ramstage-$(CONFIG_USE_DDR5) += ddr5.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR5) += ddr5.c
+ramstage-$(CONFIG_DRAM_SUPPORT_DDR5) += ddr5.c
 
-romstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
-ramstage-$(CONFIG_USE_LPDDR4) += lpddr4.c
+romstage-$(CONFIG_DRAM_SUPPORT_LPDDR4) += lpddr4.c
+ramstage-$(CONFIG_DRAM_SUPPORT_LPDDR4) += lpddr4.c
 
-romstage-$(CONFIG_USE_DDR4) += ddr4.c
-romstage-$(CONFIG_USE_DDR4) += rcd.c
-ramstage-$(CONFIG_USE_DDR4) += ddr4.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR4) += ddr4.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR4) += rcd.c
+ramstage-$(CONFIG_DRAM_SUPPORT_DDR4) += ddr4.c
 
-romstage-$(CONFIG_USE_DDR3) += ddr3.c
-ramstage-$(CONFIG_USE_DDR3) += ddr3.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR3) += ddr3.c
+ramstage-$(CONFIG_DRAM_SUPPORT_DDR3) += ddr3.c
 
-romstage-$(CONFIG_USE_DDR2) += ddr2.c
-ramstage-$(CONFIG_USE_DDR2) += ddr2.c
+romstage-$(CONFIG_DRAM_SUPPORT_DDR2) += ddr2.c
+ramstage-$(CONFIG_DRAM_SUPPORT_DDR2) += ddr2.c

src/mainboard/hardkernel/odroid-h4/Kconfig

@@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SUPERIO_ITE_IT8613E
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 
 config MAINBOARD_DIR
 	default "hardkernel/odroid-h4"

src/mainboard/protectli/vault_adl_p/Kconfig

@@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select INTEL_GMA_HAVE_VBT
 	select MEMORY_MAPPED_TPM
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 
 config MAINBOARD_DIR
 	default "protectli/vault_adl_p"

src/northbridge/amd/pi/00730F01/Kconfig

@@ -2,7 +2,7 @@
 
 config NORTHBRIDGE_AMD_PI_00730F01
 	bool
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 
 if NORTHBRIDGE_AMD_PI_00730F01
 

src/northbridge/intel/gm45/Kconfig

@@ -8,8 +8,8 @@ config NORTHBRIDGE_INTEL_GM45
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_SSC_ALTERNATE_REF
 	select HAVE_X86_64_SUPPORT
-	select USE_DDR3
-	select USE_DDR2
+	select DRAM_SUPPORT_DDR3
+	select DRAM_SUPPORT_DDR2
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_GM45

src/northbridge/intel/haswell/Kconfig

@@ -6,7 +6,7 @@ config NORTHBRIDGE_INTEL_HASWELL
 	select CACHE_MRC_SETTINGS
 	select INTEL_DDI
 	select INTEL_GMA_ACPI
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 
 if NORTHBRIDGE_INTEL_HASWELL
 

src/northbridge/intel/i945/Kconfig

@@ -8,7 +8,7 @@ config NORTHBRIDGE_INTEL_I945
 	select INTEL_GMA_SSC_ALTERNATE_REF
 	select INTEL_EDID
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
-	select USE_DDR2
+	select DRAM_SUPPORT_DDR2
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_I945

src/northbridge/intel/ironlake/Kconfig

@@ -8,7 +8,7 @@ config NORTHBRIDGE_INTEL_IRONLAKE
 	select INTEL_GMA_ACPI
 	select CACHE_MRC_SETTINGS
 	select HAVE_DEBUG_RAM_SETUP
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_IRONLAKE

src/northbridge/intel/pineview/Kconfig

@@ -8,8 +8,8 @@ config NORTHBRIDGE_INTEL_PINEVIEW
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
 	select INTEL_GMA_ACPI
-	select USE_DDR3
-	select USE_DDR2
+	select DRAM_SUPPORT_DDR3
+	select DRAM_SUPPORT_DDR2
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_PINEVIEW

src/northbridge/intel/sandybridge/Kconfig

@@ -7,7 +7,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select HAVE_DEBUG_RAM_SETUP
 	select INTEL_GMA_ACPI
 	select NEED_SMALL_2MB_PAGE_TABLES
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 
 if NORTHBRIDGE_INTEL_SANDYBRIDGE
 

src/northbridge/intel/x4x/Kconfig

@@ -8,8 +8,8 @@ config NORTHBRIDGE_INTEL_X4X
 	select CACHE_MRC_SETTINGS
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select HAVE_X86_64_SUPPORT
-	select USE_DDR3
-	select USE_DDR2
+	select DRAM_SUPPORT_DDR3
+	select DRAM_SUPPORT_DDR2
 	select NEED_SMALL_2MB_PAGE_TABLES
 
 if NORTHBRIDGE_INTEL_X4X

src/soc/amd/cezanne/Kconfig

@@ -80,8 +80,8 @@ config SOC_AMD_CEZANNE
 	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
 	select UDK_2017_BINDING
-	select USE_DDR4
-	select USE_LPDDR4
+	select DRAM_SUPPORT_DDR4
+	select DRAM_SUPPORT_LPDDR4
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

src/soc/amd/common/fsp/dmi.c

@@ -23,11 +23,11 @@
  */
 static uint16_t ddr_speed_mhz_to_reported_mts(uint16_t ddr_type, uint16_t speed)
 {
-	if (CONFIG(USE_DDR4) && ddr_type == MEMORY_TYPE_DDR4)
+	if (CONFIG(DRAM_SUPPORT_DDR4) && ddr_type == MEMORY_TYPE_DDR4)
 		return ddr4_speed_mhz_to_reported_mts(speed);
-	else if (CONFIG(USE_LPDDR4) && ddr_type == MEMORY_TYPE_LPDDR4)
+	else if (CONFIG(DRAM_SUPPORT_LPDDR4) && ddr_type == MEMORY_TYPE_LPDDR4)
 		return lpddr4_speed_mhz_to_reported_mts(speed);
-	else if (CONFIG(USE_DDR5) && (ddr_type == MEMORY_TYPE_DDR5 ||
+	else if (CONFIG(DRAM_SUPPORT_DDR5) && (ddr_type == MEMORY_TYPE_DDR5 ||
 			ddr_type == MEMORY_TYPE_LPDDR5))
 		return ddr5_speed_mhz_to_reported_mts(speed);
 

src/soc/amd/glinda/Kconfig

@@ -84,7 +84,7 @@ config SOC_AMD_GLINDA
 	select SOC_FILL_CPU_CACHE_INFO
 	select SSE2
 	select UDK_2017_BINDING
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

src/soc/amd/mendocino/Kconfig

@@ -86,7 +86,7 @@ config SOC_AMD_REMBRANDT_BASE
 	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
 	select UDK_2017_BINDING
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

src/soc/amd/phoenix/Kconfig

@@ -73,7 +73,7 @@ config SOC_AMD_PHOENIX_BASE
 	select SOC_AMD_COMMON_BLOCK_XHCI
 	select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
 	select SSE2
-	select USE_DDR5
+	select DRAM_SUPPORT_DDR5
 	select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
 	select VBOOT_X86_SHA256_ACCELERATION if VBOOT
 	select X86_AMD_FIXED_MTRRS

src/soc/amd/picasso/Kconfig

@@ -70,7 +70,7 @@ config SOC_AMD_PICASSO
 	select SOC_AMD_SUPPORTS_WARM_RESET
 	select SSE2
 	select UDK_2017_BINDING
-	select USE_DDR4
+	select DRAM_SUPPORT_DDR4
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

src/soc/amd/stoneyridge/Kconfig

@@ -46,7 +46,7 @@ config SOC_AMD_STONEYRIDGE
 	select SOC_AMD_COMMON_LATE_SMM_LOCKING
 	select SSE2
 	select TSC_SYNC_LFENCE
-	select USE_DDR4
+	select DRAM_SUPPORT_DDR4
 	select X86_AMD_FIXED_MTRRS
 	help
 	  AMD support for SOCs in Family 15h Models 60h-6Fh and Models 70h-7Fh.

src/soc/intel/baytrail/Kconfig

@@ -32,7 +32,7 @@ config SOC_INTEL_BAYTRAIL
 	select CPU_INTEL_COMMON
 	select CPU_HAS_L2_ENABLE_MSR
 	select TCO_SPACE_NOT_YET_SPLIT
-	select USE_DDR3
+	select DRAM_SUPPORT_DDR3
 	select NEED_SMALL_2MB_PAGE_TABLES
 	help
 	  Bay Trail M/D part support.

src/soc/intel/snowridge/Kconfig

@@ -27,7 +27,7 @@ config SOC_INTEL_SNOWRIDGE
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 
 	## Device
-	select USE_DDR4
+	select DRAM_SUPPORT_DDR4
 
 	## Drivers
 	select CACHE_MRC_SETTINGS