sb/intel: Add soc/gpio.h

In order to use the common gpio.h header file typedef gpio_t in
soc/gpio.h for Intel common code, Intel lynxpoint and Intel broadwell.

Change-Id: I2049a2cfd75c60d00bdd564b294808760b6aff7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Patrick Rudolph 2025-07-13 12:03:05 +02:00 committed by Matt DeVillier
commit 2d7891abe2
5 changed files with 40 additions and 3 deletions

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@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _BROADWELL_GPIO_H_
#define _BROADWELL_GPIO_H_
#include <stdint.h>
typedef uint32_t gpio_t;
#endif /* _BROADWELL_GPIO_H_ */

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@ -53,3 +53,9 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO),y)
CPPFLAGS_common += -I$(src)/southbridge/intel/common/include
endif

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@ -4,6 +4,7 @@
#define INTEL_COMMON_GPIO_H
#include <stdint.h>
#include <soc/gpio.h>
/* ICH7 GPIOBASE */
#define GPIO_USE_SEL 0x00
@ -31,9 +32,6 @@
#define GPIO_NO_INVERT 0
#define GPIO_INVERT 1
#define GPIO_LEVEL_LOW 0
#define GPIO_LEVEL_HIGH 1
#define GPIO_NO_BLINK 0
#define GPIO_BLINK 1

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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SB_INTEL_COMMON_GPIO_BANKS_H
#define SB_INTEL_COMMON_GPIO_BANKS_H
#include <stdint.h>
typedef uint32_t gpio_t;
#define GPIO_LEVEL_LOW 0
#define GPIO_LEVEL_HIGH 1
#endif /* SB_INTEL_COMMON_GPIO_BANKS_H */

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@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SB_INTEL_LYNXPOINT_GPIO_BANKS_H
#define SB_INTEL_LYNXPOINT_GPIO_BANKS_H
#include <stdint.h>
typedef uint32_t gpio_t;
#endif /* SB_INTEL_LYNXPOINT_GPIO_BANKS_H */